diff options
| author | Han Xu <b45815@freescale.com> | 2015-06-10 17:14:01 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:02:38 -0600 |
| commit | 8308b1df9013546b47073fb3088237f55f03d88b (patch) | |
| tree | 5ad45edaf7bef272bb41a688bfb7b7c72526f854 /arch/arm/boot/dts/imx7d-sdb-qspi.dts | |
| parent | 3789ec9f5fcd96cf87a186c219a55d62e9694ecd (diff) | |
MLK-11087: mtd:qspi: support DDR Quad mode for Macronix mx25l51245g
Enable DDR quad mode for Macronix qspi chip mx25l51245g by setting Quad
bit in status register and enabling in dts file.
The LUT for SPINOR_OP_READ_1_4_4_D was initially designed for Spansion
qspi chip, so there is one cycle for "mode" after address and before
dummy. While Macronix qspi chip doesn't have this feature, so we just
take off one cycle in dts file to bypass this problem.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked and merge from commit e03fdad1c7713a7db70112e00c4ae96848accd34)
Diffstat (limited to 'arch/arm/boot/dts/imx7d-sdb-qspi.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx7d-sdb-qspi.dts | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7d-sdb-qspi.dts b/arch/arm/boot/dts/imx7d-sdb-qspi.dts index 83b040170f2f..d49ddf2e9af4 100644 --- a/arch/arm/boot/dts/imx7d-sdb-qspi.dts +++ b/arch/arm/boot/dts/imx7d-sdb-qspi.dts @@ -39,6 +39,8 @@ #size-cells = <1>; compatible = "macronix,mx25l51245g"; spi-max-frequency = <29000000>; + /* take off one dummy cycle */ + spi-nor,ddr-quad-read-dummy = <5>; reg = <0>; }; }; |