MLK-12035 dts: imx7d-sdb-revb: add i.MX7d sdb revb support

Base on i.MX7d sdb revb board change list, below modules has changed:
 - enet2 and epdc enable pin
 - usb_otg2 pwr enable pin
 - ov5647_mipi pwr pin
 - tsc2046 touch pendown pin
 - uart5 tx/rx pins
 - sensor INT pin
 - pcie power is controlled by por_b, not gpio_spi pin6
 - hdmi audio change to SAI3 from SAI1

The patch add the changes for revb, and keep the original functions for
reva board. Remove redundancy sim and enet dts files to avoid excessive
dts file for reva and revb.

After the patch, there have below diff:
- default dts file: imx7d-sdb.dts for revb board, imx7d-sdb-reva.dts for reva board
- remove enet, sim extended dts files, so these modules are enabled in default dts
  file for reva and revb board.

The change of expanded dts due to pin confliction:
- Keep the original expanded name of dts file for revb board, add suffix "-reva" in dts
  file name for reva board.
- Like:
  hdmi/codec audio:
    hdmi audio and wm8960 codec are enabled in default dts file for revb board,
    no extended dts files to separate them.
    Keep original extended dts files for reva board:
	imx7d-sdb-reva-hdmi-audio.dts
	imx7d-sdb-reva-wm8960.dts
  epdc:
    imx7d-sdb-epdc.dts is for revb board, imx7d-sdb-reva-epdc.dts is for reva board.
  gpmi-weim:
    imx7d-sdb-gpmi-weim.dtsi for revb, imx7d-sdb-reva-gpmi-weim.dtsi for reva.
  m4:
    imx7d-sdb-m4.dts for revb, imx7d-sdb-reva-m4.dts for reva.
  qspi:
    imx7d-sdb-qspi.dts for revb, imx7d-sdb-reva-qspi.dts for reva.
  touchscreen:
    imx7d-sdb-touch.dts for revb, imx7d-sdb-reva-touch.dts for reva.

Cherry picked from commit: 2be1a236696d, and disable sai3 since there have many
Transmit underrun on kernel 4.1.

Signed-off-by: Fugang Duan <B38611@freescale.com>
Acked-by: Robby Cai <robby.cai@nxp.com>
Acked-by: Gao Pan <pandy.gao@nxp.com>
Acked-by: Peter Chen <peter.chen@freescale.com>
Acked-by: Chen Bough <Haibo.Chen@freescale.com>

Conflicts:
	arch/arm/boot/dts/Makefile
	arch/arm/boot/dts/imx7d-sdb-epdc.dts
	arch/arm/boot/dts/imx7d-sdb-gpmi-weim.dtsi
	arch/arm/boot/dts/imx7d-sdb-m4.dts
	arch/arm/boot/dts/imx7d-sdb-reva-epdc.dts
	arch/arm/boot/dts/imx7d-sdb-touch.dts
	arch/arm/boot/dts/imx7d-sdb.dts

1 files changed, 49 insertions, 30 deletions

diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index b30c8f09e2bb..5a9bea0c4f47 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -59,7 +59,7 @@
 		compatible = "fsl,imx7d-sdb-sii902x",
 			   "fsl,imx-audio-sii902x";
 		model = "sii902x-audio";
-		cpu-dai = <&sai1>;
+		cpu-dai = <&sai3>;
 		hdmi-controler = <&sii902x>;
 	};
 
@@ -107,18 +107,7 @@
 			regulator-name = "usb_otg2_vbus";
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
-			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
-			enable-active-high;
-		};
-
-		reg_pcie: regulator@2 {
-			compatible = "regulator-fixed";
-			reg = <2>;
-			regulator-name = "MPCIE_3V3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			gpio = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
-			regulator-always-on;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
 
@@ -174,11 +163,11 @@
 
 &epdc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_epdc0>;
+	pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_epdc0_en>;
 	V3P3-supply = <&V3P3_reg>;
 	VCOM-supply = <&VCOM_reg>;
 	DISPLAY-supply = <&DISPLAY_reg>;
-	en-gpios = <&gpio_spi 5 0>;
+	en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 	status = "disabled";
 };
 
@@ -217,7 +206,8 @@
 
 &fec2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet2>;
+	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>;
+	pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
@@ -481,7 +471,7 @@
 		clocks = <&clks IMX7D_CLK_DUMMY>;
 		clock-names = "csi_mclk";
 		csi_id = <0>;
-		pwn-gpios = <&gpio_spi 7 GPIO_ACTIVE_HIGH>;
+		pwn-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
 		mclk = <24000000>;
 		mclk_source = <0>;
 		port {
@@ -506,8 +496,7 @@
 	imx7d-sdb {
 		pinctrl_hog_1: hoggrp-1 {
 			fsl,pins = <
-				MX7D_PAD_UART3_CTS_B__GPIO4_IO7	0x14
-				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23	 0x80000000  /* bt reg on */
+				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23	0x80000000  /* bt reg on */
 			>;
 		};
 
@@ -561,6 +550,12 @@
 			>;
 		};
 
+		pinctrl_enet2_epdc0_en: enet2_epdc0_grp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO04__GPIO1_IO4		0x59
+			>;
+		};
+
                 pinctrl_epdc0: epdcgrp0 {
                         fsl,pins = <
 				MX7D_PAD_EPDC_DATA00__EPDC_DATA0  0x2
@@ -589,8 +584,6 @@
 				MX7D_PAD_EPDC_GDOE__EPDC_GDOE     0x2
 				MX7D_PAD_EPDC_GDRL__EPDC_GDRL     0x2
 				MX7D_PAD_EPDC_GDSP__EPDC_GDSP     0x2
-				MX7D_PAD_EPDC_BDR0__EPDC_BDR0     0x2
-				MX7D_PAD_EPDC_BDR1__EPDC_BDR1     0x2
                         >;
                 };
 
@@ -719,6 +712,15 @@
 			>;
 		};
 
+		pinctrl_sai3: sai3grp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO03__SAI3_MCLK         0x1f
+				MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK   0x1f
+				MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC     0x1f
+				MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0    0x30
+			>;
+		};
+
 		pinctrl_spi1: spi1grp {
 			fsl,pins = <
 				MX7D_PAD_GPIO1_IO09__GPIO1_IO9	0x59
@@ -745,7 +747,7 @@
 
 		pinctrl_tsc2046_pendown: tsc2046_pendown {
 			fsl,pins = <
-				MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59
+				MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x59
 			>;
 		};
 
@@ -758,10 +760,8 @@
 
 		pinctrl_uart5: uart5grp {
 			fsl,pins = <
-				MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
-				MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
-				MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
-				MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
+				MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX	0x79
+				MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX	0x79
 			>;
 		};
 
@@ -769,8 +769,6 @@
 			fsl,pins = <
 				MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79
 				MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79
-				MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x79
-				MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x79
 			>;
 		};
 
@@ -792,6 +790,12 @@
 			>;
 		};
 
+		pinctrl_usbotg2_pwr_1: usbotg2-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_CTS_B__GPIO4_IO7	0x14
+			>;
+		};
+
 		pinctrl_usdhc1: usdhc1grp {
 			fsl,pins = <
 				MX7D_PAD_SD1_CMD__SD1_CMD		0x59
@@ -960,6 +964,16 @@
 	status = "okay";
 };
 
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
+			  <&clks IMX7D_SAI3_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <0>, <36864000>;
+	status = "disabled";
+};
+
 &sdma {
 	status = "okay";
 };
@@ -972,7 +986,7 @@
 
 &iomuxc_lpsr {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_hog_2>;
+	pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>;
 
 	imx7d-sdb {
 		pinctrl_hog_2: hoggrp-2 {
@@ -987,6 +1001,12 @@
 			>;
 		};
 
+		pinctrl_usbotg2_pwr_2: usbotg2-2 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
+			>;
+		};
+
 		pinctrl_wdog: wdoggrp {
 			fsl,pins = <
 				MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
@@ -1018,7 +1038,6 @@
 	pinctrl-0 = <&pinctrl_uart5>;
 	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
 	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
-	fsl,uart-has-rtscts;
 	/* for DTE mode, add below change */
 	/* fsl,dte-mode; */
 	/* pinctrl-0 = <&pinctrl_uart5dte>; */