MLK-11316-4 video: mxc ipuv3 fb: Change on-the-fly switch mechanism for PRE workaround

In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.

Instead of setting the PRE_CTRL register any time we want to do on-the-fly
switch(PRE keeps working before and after the switch), we change to set the
register in the on-the-fly configuration interrupt(EOF) handler.  This way,
we may avoid encountering the problematic PRE automatic writing cycle for sure.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 6218cbcf34f5fb7910a824a8d31cc58819d0bd00)

0 files changed, 0 insertions, 0 deletions