diff options
author | Peng Fan <peng.fan@nxp.com> | 2016-01-13 14:50:29 +0800 |
---|---|---|
committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:24:10 +0800 |
commit | 853f34abf77245d39bcff99139da2b791697c68e (patch) | |
tree | ca01995260135157d33ec6cb266d1bd6bcf7a0aa /arch/arm/boot/dts/imx7d-sdb.dts | |
parent | 51b478d651e6be08f39e7f7dbae0edda278149a4 (diff) |
MLK-12189 imx: mx7d correct iomux error for SAI3 and ENET2_EN
pinmux settings using GPIO1_IO0[0-7] should use iomuxc_lpsr,
but not iomuxc. If use iomuxc, you will set wrong register
and may impact other functions.
Without this patch, SAI3_MCLK use GPIO1_IO03 pinmux and impacts
QSPI function.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7d-sdb.dts')
-rw-r--r-- | arch/arm/boot/dts/imx7d-sdb.dts | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 39ec63b9fca4..5be190cf37d6 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -620,7 +620,7 @@ &sai3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, <&clks IMX7D_SAI3_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; @@ -661,6 +661,18 @@ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 >; }; + + pinctrl_enet2_epdc0_en: enet2_epdc0_grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000 + >; + }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; }; }; @@ -859,13 +871,6 @@ >; }; - - pinctrl_enet2_epdc0_en: enet2_epdc0_grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000 - >; - }; - pinctrl_epdc0: epdcgrp0 { fsl,pins = < MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 @@ -1012,7 +1017,6 @@ pinctrl_sai3: sai3grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 |