diff options
| author | Leonard Crestez <leonard.crestez@nxp.com> | 2018-02-28 17:55:22 +0200 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:23:56 +0800 |
| commit | 963335029d93a77b89ca73b407a23f710597acc9 (patch) | |
| tree | 9ad3f91b2ca74943cc1b7e6820bf8b437fd5f7fb /arch/arm/boot/dts/imx7d-sdb.dts | |
| parent | 1564a7312f530576ce84acccb450f95818ff4569 (diff) | |
MLK-11373: ARM: dts: i.MX7d: add gpmi nand support for 7d-sdb board
Add gpmi nand support on i.MX7D sdb board.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
During 4.14 rebase found that imx7s.dtsi already has a gpmi-nand node
added by upstream, preferred that one and skipped the definition in
imx7d.dtsi. The definitions differed on clocks.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7d-sdb.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx7d-sdb.dts | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 92e86a64823d..32846ea55983 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -750,6 +750,13 @@ fsl,ext-reset-output; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -860,6 +867,28 @@ >; }; + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f |