diff options
| author | Fugang Duan <b38611@freescale.com> | 2015-08-18 09:36:46 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:21:52 +0800 |
| commit | bb9b34157276a45187b63dabca7bf863b7cbe78b (patch) | |
| tree | a955696138ccd3243c3ea3129af29a9d92a1314e /arch/arm/boot/dts/imx7d-sdb.dts | |
| parent | 7610f32653dc0fa718cb275a795103703975a2c2 (diff) | |
MLK-10462 ARM: dts: imx7d-sdb: enable uart5 node
Enable uart5 for GPS
Signed-off-by: Fugang Duan <B38611@freescale.com>
Upstream already added uart6 in 4.14
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7d-sdb.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx7d-sdb.dts | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 14db7f3e4ec2..101fcd82b049 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -429,6 +429,18 @@ status = "okay"; }; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ + status = "okay"; +}; + &uart6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart6>; @@ -567,7 +579,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 /* bt reg on */ >; }; @@ -674,6 +686,15 @@ >; }; + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x79 + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x79 + >; + }; + pinctrl_uart6: uart6grp { fsl,pins = < MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 |