diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-04-22 09:23:41 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:13 +0800 |
| commit | 7052d5ef55fff8a08c2f0deef46132e781c2821a (patch) | |
| tree | 6ab1ca92fe2232311d05d181dd8caeddc2d869c4 /arch/arm/boot/dts/imx7s.dtsi | |
| parent | b92e16830ee73e098e7d057e75e286e33f36f723 (diff) | |
ARM: dts: imx7d: add low power support
This patch adds low power mode support for i.MX7D, including
FastMix off feature support, low power idle support and A7-M4
AMP power management support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7s.dtsi | 37 |
1 files changed, 13 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index b4ac51062f77..50abcc811146 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -53,19 +53,6 @@ #address-cells = <1>; #size-cells = <0>; - idle-states { - entry-method = "psci"; - - cpu_sleep_wait: cpu-sleep-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <50>; - min-residency-us = <1000>; - }; - }; - cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; @@ -73,7 +60,6 @@ clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; - cpu-idle-states = <&cpu_sleep_wait>; }; }; @@ -158,15 +144,6 @@ clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; }; - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&intc>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -316,6 +293,17 @@ <0x31006000 0x2000>; }; + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <8000000>; + }; + aips1: aips-bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -628,7 +616,7 @@ }; src: src@30390000 { - compatible = "fsl,imx7d-src", "syscon"; + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; @@ -641,6 +629,7 @@ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <3>; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; #power-domain-cells = <1>; pgc { |