summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/qcom-msm8960-cdp.dts
diff options
context:
space:
mode:
authorKumar Gala <galak@codeaurora.org>2014-05-28 12:09:53 -0500
committerKumar Gala <galak@codeaurora.org>2014-05-29 10:35:00 -0500
commit665c9c03f6405bdec6e9629d9dfa795c2124a5a2 (patch)
tree9a03e3222333f419c761ab74cf2b5f921e69bc6d /arch/arm/boot/dts/qcom-msm8960-cdp.dts
parentba08220aa81e757491a3665c28df7eaa954128dc (diff)
ARM: dts: qcom: Update msm8960 device trees
* Move SoC peripherals into an SoC container node * Move serial enabling into board file (qcom-msm8960-cdp.dts) * Cleanup cpu node to match binding spec, enable-method and compatible should be per cpu, not part of the container * Drop interrupts property from l2-cache node as its not part of the binding spec * Add GSBI node and configuration of GSBI controller Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8960-cdp.dts')
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88315f6..8f75cc4c8340 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,14 @@
/ {
model = "Qualcomm MSM8960 CDP";
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+
+ soc {
+ gsbi@16400000 {
+ status = "ok";
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ serial@16440000 {
+ status = "ok";
+ };
+ };
+ };
};