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| author | Olof Johansson <olof@lixom.net> | 2015-01-21 17:00:47 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-01-21 17:00:47 -0800 |
| commit | e42da8a1462ab4175acdaf9b2f00f00bf4d81d42 (patch) | |
| tree | 3b611a8839e620f07f12ae00c8da339b5092aac0 /arch/arm/boot/dts/r8a7791.dtsi | |
| parent | 6937dbffc750c0379ea08880469015a3f68f872d (diff) | |
| parent | fbaa5e694a1240c5f6b829b1e17652e4e228ee12 (diff) | |
Merge tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Second Round of Renesas ARM Based SoC DT Updates for v3.20" from Simon
Horman:
* Support Renesas memory controllers
* Add SRC interrupt number on r8a779~ and r8a7791 SoCs
* Fix MSTP8 input clocks on r8a7791 SoC
* Add PM domain support to r8a7740
* Add DT bindings for the R-Mobile System Controller
* Use Add sh73a0-specific FSI2 compatible property
* tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
PM / Domains: R-Mobile SYSC: Document SH-Mobile AG5 (sh73a0) binding
ARM: shmobile: sh73a0 dtsi: Add memory-controller nodes
ARM: shmobile: r8a7740 dtsi: Add memory-controller node
ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodes
ARM: shmobile: Add DT bindings for Renesas memory controllers
ARM: shmobile: r8a7791: add SRC interrupt number on DTSI
ARM: shmobile: r8a7790: add SRC interrupt number on DTSI
ARM: shmobile: r8a7791: fix MSTP8 input clocks
ARM: shmobile: r8a7740 dtsi: Add PM domain support
PM / Domains: Add DT bindings for the R-Mobile System Controller
ARM: shmobile: sh73a0 dtsi: Add SoC-specific FSI2 compatible property
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 5769faf17f28..e35812a0d8d4 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1154,7 +1154,7 @@ mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, + clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; clock-indices = < @@ -1425,16 +1425,16 @@ }; rcar_sound,src { - src0: src@0 { }; - src1: src@1 { }; - src2: src@2 { }; - src3: src@3 { }; - src4: src@4 { }; - src5: src@5 { }; - src6: src@6 { }; - src7: src@7 { }; - src8: src@8 { }; - src9: src@9 { }; + src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; }; + src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; }; + src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; }; + src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; }; + src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; }; + src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; }; + src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; }; + src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; }; + src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; }; + src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; }; }; rcar_sound,ssi { |