diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-07-05 00:22:38 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-08-08 12:52:56 +0200 |
| commit | 08cafff67e8881e1622068924aaab3c3aa052b0b (patch) | |
| tree | ad563d3da28c5bc0b69540c4986c2c61d83aee81 /arch/arm/boot/dts/r8a7792.dtsi | |
| parent | 63359c2ddc86bded339f38bde504994f123ebd63 (diff) | |
ARM: dts: r8a7792: add EtherAVB clocks
Add the EtherAVB clock and its parent, HP clock to the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index d5ab9474297e..f97b034da35f 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -471,6 +471,13 @@ clock-div = <6>; clock-mult = <1>; }; + hp_clk: hp { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + }; p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -538,6 +545,15 @@ clock-output-names = "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0"; }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&hp_clk>; + #clock-cells = <1>; + clock-indices = <R8A7792_CLK_ETHERAVB>; + clock-output-names = "etheravb"; + }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; |