diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-06-21 01:31:01 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-06-30 14:26:14 +0200 |
| commit | 8fd763c75c3ab8e72e5d7f0d4c53531e6ff76197 (patch) | |
| tree | 2f89004faf54a154e5315b3218a1488079a4db75 /arch/arm/boot/dts/r8a7792.dtsi | |
| parent | 65b133cd79cfde9f4e0157deb0e0f88f92811ad3 (diff) | |
ARM: dts: r8a7792: add SMP support
Add the device tree nodes for the Advanced Power Management Unit (APMU)
and the second Cortex-A15 CPU core.
Use the "enable-method" prop to point out that the APMU should be used
for the SMP support.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7792.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index ad895f8b2353..75256ef4a04d 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -21,6 +21,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -32,6 +33,15 @@ next-level-cache = <&L2_CA15>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1000000000>; + power-domains = <&sysc R8A7792_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + L2_CA15: cache-controller@0 { compatible = "cache"; reg = <0>; @@ -49,6 +59,12 @@ #size-cells = <2>; ranges; + apmu@e6152000 { + compatible = "renesas,r8a7792-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; |