diff options
| author | Ulrich Hecht <ulrich.hecht+renesas@gmail.com> | 2016-04-18 18:02:56 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-04-25 14:10:10 +1000 |
| commit | fc9ee228f5005437b9fdb1b85804b6d3f8d497be (patch) | |
| tree | 7c05a50c412bf2c80169e880c908054bfd7f5066 /arch/arm/boot/dts/r8a7793.dtsi | |
| parent | 21c7d0fcbe10a1a81fb791a9bdcca2381bc16c15 (diff) | |
ARM: dts: r8a7793: Add SDHI controllers
Same as on r8a7791.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7793.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7793.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index bddc31283bd9..6186179fd66d 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -507,6 +507,39 @@ reg = <0 0xe6060000 0 0x250>; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7793"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7793"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7793"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7793", "renesas,rcar-gen2-scifa", "renesas,scifa"; |