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authorBeniamino Galvani <b.galvani@gmail.com>2014-06-26 20:03:41 +0200
committerHeiko Stuebner <heiko@sntech.de>2014-07-27 00:24:16 +0200
commit550c7f4e6377cf5093b1b8d6b99cde2506bfea23 (patch)
tree941516fdcc50b41de51cc97b05a9153103b307c2 /arch/arm/boot/dts/rk3066a.dtsi
parent69667ca2c4ad5bd346fb694a68e676fa46b2fba0 (diff)
ARM: dts: rockchip: add pwm nodes
This adds the necessary nodex and pinctrl settings for the Rockchip PWM-driver. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Modified to use the new clock defines and added rk3066 pins. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3066a.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi44
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 18e802c08a91..9c34da4d8aad 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -214,6 +214,30 @@
};
};
+ pwm0 {
+ pwm0_out: pwm0-out {
+ rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_out: pwm1-out {
+ rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_out: pwm2-out {
+ rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_out: pwm3-out {
+ rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
@@ -362,6 +386,26 @@
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_out>;
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_out>;
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_out>;
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_out>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;