diff options
| author | Heiko Stuebner <heiko.stuebner@bq.com> | 2018-10-15 14:46:19 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-11-27 15:11:39 +0100 |
| commit | 66dc478a283ca32a9d9c40a53e97fad4d408757c (patch) | |
| tree | b2bd37270042f3008d3b2195e1332c2cdfe7a36b /arch/arm/boot/dts/rk3188.dtsi | |
| parent | 0222aac4486e7bf5b37defa7fd03e3b2c52fe2be (diff) | |
ARM: dts: rockchip: add phandles to secondary cpu cores
Add phandles to secondary cpu cores as we may need to reference these
down the road as well.
Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
Diffstat (limited to 'arch/arm/boot/dts/rk3188.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3188.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index f1f7a36b46d4..4acb501dd3f8 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -28,7 +28,7 @@ operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; @@ -36,7 +36,7 @@ operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; @@ -44,7 +44,7 @@ operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; |