diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2015-06-19 16:31:14 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2015-07-06 00:46:20 +0200 |
| commit | 1a1b698b115467242303daf5fe1d3c9886c2fa17 (patch) | |
| tree | ba614399d44f8f4cccdf040a811e30e3cccc39db /arch/arm/boot/dts/rk3288.dtsi | |
| parent | 270c7b18d7c0f17cfda2bbdafba25ef2f885f9a5 (diff) | |
ARM: dts: rockchip: fix rk3288 watchdog irq
The watchdog irq is actually SPI 79, which translates to the original
111 in the manual where the SPI irqs start at 32.
The current dw_wdt driver does not use the irq at all, so this issue
never surfaced. Nevertheless fix this for a time we want to use the irq.
Fixes: 2ab557b72d46 ("ARM: dts: rockchip: add core rk3288 dtsi")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 47476d5d5227..22e9221877c6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -628,7 +628,7 @@ compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; reg = <0xff800000 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; |