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authorKarim BEN BELGACEM <karim.ben-belgacem@st.com>2015-03-18 18:21:00 +0100
committerMaxime Coquelin <maxime.coquelin@st.com>2015-04-30 15:36:19 +0200
commitd90accb913a7a72172ec6b82f8b8766d9c9bf8bf (patch)
tree131daa2d96f41d062751a460f47af4fc28aa2483 /arch/arm/boot/dts/stih407-pinctrl.dtsi
parent358764f306242bf2b3d71693b04b05e0b75718ae (diff)
ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35
This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM <karim.ben-belgacem@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stih407-pinctrl.dtsi')
-rw-r--r--arch/arm/boot/dts/stih407-pinctrl.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 402844cb3152..0a754f275212 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -104,6 +104,7 @@
#interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO5";
+ st,retime-pin-mask = <0x3f>;
};
rc {
@@ -519,6 +520,7 @@
#interrupt-cells = <2>;
reg = <0x5000 0x100>;
st,bank-name = "PIO35";
+ st,retime-pin-mask = <0x7f>;
};
i2c4 {