diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-02-28 17:40:23 +0100 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2014-02-28 10:23:44 -0700 |
| commit | d72be031b3ceeae5a4761e400af1ac60ca313449 (patch) | |
| tree | 32c2544acc3ad55917a1ef97f87c35b18d930601 /arch/arm/boot/dts/tegra124.dtsi | |
| parent | ad6be7d1146daa90be90e924fd5fb07a22d8ffda (diff) | |
ARM: tegra: Add Tegra124 eDP support
The SOR block on Tegra124 can be used standalone to drive LVDS panels or
used in conjunction with the DPAUX block to support eDP.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 26dfe09e8410..dd5330f01e13 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -48,6 +48,32 @@ nvidia,head = <1>; }; + + sor@54540000 { + compatible = "nvidia,tegra124-sor"; + reg = <0x54540000 0x00040000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA124_CLK_PLL_DP>, + <&tegra_car TEGRA124_CLK_CLK_M>; + clock-names = "sor", "parent", "dp", "safe"; + resets = <&tegra_car 182>; + reset-names = "sor"; + status = "disabled"; + }; + + dpaux@545c0000 { + compatible = "nvidia,tegra124-dpaux"; + reg = <0x545c0000 0x00040000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_DPAUX>, + <&tegra_car TEGRA124_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 181>; + reset-names = "dpaux"; + status = "disabled"; + }; }; gic: interrupt-controller@50041000 { |