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authorCatalin Marinas <catalin.marinas@arm.com>2009-07-24 12:32:52 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2009-07-24 12:32:52 +0100
commit88987ef91b99cf99bc5d167caeb31d4958fbf931 (patch)
tree95557c2fe408ad98d9547025ae98b0d0c1377aa2 /arch/arm/boot
parent4be3bd7849165e7efa6b0b35a23d6a3598d97465 (diff)
Thumb-2: Add some .align statements to the .S files
Since the Thumb-2 instructions can be 16-bit wide, data in the .text sections may not be aligned to a 32-bit word and this leads to unaligned exceptions. This patch does not affect the ARM code generation. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/compressed/head.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 4515728c5345..82f5fcfd9567 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -291,6 +291,7 @@ wont_overwrite: mov r0, r4
bl decompress_kernel
b call_kernel
+ .align 2
.type LC0, #object
LC0: .word LC0 @ r1
.word __bss_start @ r2
@@ -589,6 +590,7 @@ call_cache_fn: adr r12, proc_types
* methods. Writeback caches _must_ have the flush method
* defined.
*/
+ .align 2
.type proc_types,#object
proc_types:
.word 0x41560600 @ ARM6/610
@@ -945,6 +947,7 @@ __armv3_mpu_cache_flush:
* memory, which again must be relocatable.
*/
#ifdef DEBUG
+ .align 2
.type phexbuf,#object
phexbuf: .space 12
.size phexbuf, . - phexbuf