diff options
| author | Xin Xie <xxie@nvidia.com> | 2011-04-28 16:51:28 -0700 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-05-25 15:14:16 -0700 |
| commit | 7d4b75fd31d2be1f287bf97eac6e62519978b206 (patch) | |
| tree | 44225b70e3a5c7c3783c249a3041ccd54cc2c98b /arch/arm/include | |
| parent | b3f98b67dc95202c33458a36004188ade991f641 (diff) | |
Revert "HACK stay compatible with the emulated TLS register HACK"
This reverts commit f00c8f71dae5a16b7fab0e77fc8b32feac9d38a7.
We need enable the SWP() emulation which depend on removing domain switching
on ARM kernel. Emulated TLS register requires the user space page mapped as
R/W in kernel which requires domain swtiching. Remove this patch becasue the
ARM V7 has HW TLS register.
Change-Id: I8772832333cf53aaf2d5061d3b459576a737fcaa
Reviewed-on: http://git-master/r/29733
Reviewed-by: Xin Xie <xxie@nvidia.com>
Tested-by: Xin Xie <xxie@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/tls.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index 80f749368e4f..e71d6ff8d104 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -7,8 +7,6 @@ .macro set_tls_v6k, tp, tmp1, tmp2 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register - mov \tmp1, #0xffff0fff - str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 .endm .macro set_tls_v6, tp, tmp1, tmp2 @@ -17,7 +15,7 @@ mov \tmp2, #0xffff0fff tst \tmp1, #HWCAP_TLS @ hardware TLS available? mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register - str \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 + streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 .endm .macro set_tls_software, tp, tmp1, tmp2 |