diff options
| author | vdumpa <vdumpa@nvidia.com> | 2011-04-28 11:47:48 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-05-11 15:47:50 -0700 |
| commit | bb7254677307bb63817061ec245e9eed17662da6 (patch) | |
| tree | 671fca80e549b8a54dbbfd1a5fc246daa5ce9850 /arch/arm/include | |
| parent | 4b698ecb8116775ed56bda97c616918a188dfbe9 (diff) | |
ARM: errata: 727915: Background Clean & Invalidate by Way operation can cause data corruption.
PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation
(offset 0x7FC). This operation runs in background so that PL310 can handle
normal accesses while it is in progress. Under very rare circumstances,
due to this erratum, write data can be lost when PL310 treats a cacheable
write transaction during a Clean & Invalidate by Way operation.
This fix is to replace the background Clean & Invalby Way operation
by a software loop on all sets/ways. This works for r2p0 and r3p0 as well.
Change-Id: I45e841d8049a18f2dd36ce13e8ef15322f14c5d5
Reviewed-on: http://git-master/r/29690
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index d62847df3df5..112b02d06ead 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -24,9 +24,14 @@ #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L210 (1 << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) +#define L2X0_CACHE_ID_RTL_RELEASE_MASK (0x3F << 0) +#define L2X0_CACHE_ID_RTL_RELEASE_R2P0 (4<< 0) +#define L2X0_CACHE_ID_RTL_RELEASE_R3P0 (5<< 0) #define L2X0_CACHE_TYPE 0x004 #define L2X0_CTRL 0x100 #define L2X0_AUX_CTRL 0x104 +#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 +#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) #define L2X0_TAG_LATENCY_CTRL 0x108 #define L2X0_DATA_LATENCY_CTRL 0x10C #define L2X0_EVENT_CNT_CTRL 0x200 @@ -46,6 +51,8 @@ #define L2X0_CLEAN_WAY 0x7BC #define L2X0_CLEAN_INV_LINE_PA 0x7F0 #define L2X0_CLEAN_INV_LINE_IDX 0x7F8 +#define L2X0_CLEAN_INV_LINE_IDX_WAY_SHIFT 28 +#define L2X0_CLEAN_INV_LINE_IDX_INDEX_SHIFT 5 #define L2X0_CLEAN_INV_WAY 0x7FC #define L2X0_LOCKDOWN_WAY_D 0x900 #define L2X0_LOCKDOWN_WAY_I 0x904 |