diff options
| author | Marc Zyngier <(address hidden)> | 2012-02-10 16:20:26 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-03-08 14:05:33 -0800 |
| commit | 01cd745f0db07b1a130ac86ba6c33751c33d8743 (patch) | |
| tree | 51e8451a32999616d532547e7a9e5b8a227c734f /arch/arm/kernel/smp_twd.c | |
| parent | c36b6a4a17bc9e8b4407b5d960cec385d4fe180f (diff) | |
smp_twd: make sure timer is stopped before registering it
On secondary CPUs, the Timer Control Register is not reset
to a sane value before the timer is registered, and the TRM
doesn't seem to indicate any reset value either. In some cases,
the kernel will take an interrupt too early, depending on what
junk was present in the registers at reset time.
The fix is to set the Timer Control Register to 0 before
registering the clock_event_device and enabling the interrupt.
Problem seen on VE (Cortex A5) and Tegra.
Signed-off-by: Marc Zyngier <(address hidden)>
Change-Id: I52695f4f9a5c5e3a8973da7668b3b1352e60a80f
Reviewed-on: http://git-master/r/83085
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Diffstat (limited to 'arch/arm/kernel/smp_twd.c')
| -rw-r--r-- | arch/arm/kernel/smp_twd.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 1953102bec9f..47e44f21f60e 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -201,6 +201,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) else twd_calibrate_rate(); + __raw_writel(0, twd_base + TWD_TIMER_CONTROL); + clk->name = "local_timer"; clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP; |