diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2010-12-20 15:40:35 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-04-26 15:48:43 -0700 |
| commit | bedeade4c470740d2e90bbaaa0ca50cf8b0a6172 (patch) | |
| tree | 4586837d69fbb0a752662cd2febc2885b11eeef1 /arch/arm/kernel | |
| parent | fd4a3d3c3e8c745e448257601e06c999dd02d6e7 (diff) | |
ARM: Disallow DCC writes from secondary processors
An attempt to access the DCC console from secondary processors will
result in those processors hanging because the JTAG debugger can only
communicate with one core at a time. Allow DCC output only from CPU 0.
Useful for bringup, not necessarily for upstream
Original-Change-Id: I9118555438f5b72b16a2dfccd5b6f98860505d6d
Reviewed-on: http://git-master/r/13876
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I36bb0351e0899f4ad8732fe784623f7eea57dff5
Diffstat (limited to 'arch/arm/kernel')
| -rw-r--r-- | arch/arm/kernel/debug.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index 90ecfa32a226..db5c62dc9bc5 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -164,6 +164,11 @@ ENDPROC(printhex2) .ltorg ENTRY(printascii) +#if defined(CONFIG_DEBUG_ICEDCC) && defined(CONFIG_SMP) + mrc p15, 0, r3, c0, c0, 5 + ands r3, r3, #3 + movne pc, lr +#endif addruart r3, r1 b 2f 1: waituart r2, r3 @@ -180,6 +185,11 @@ ENTRY(printascii) ENDPROC(printascii) ENTRY(printch) +#if defined(CONFIG_DEBUG_ICEDCC) && defined(CONFIG_SMP) + mrc p15, 0, r3, c0, c0, 5 + ands r3, r3, #3 + movne pc, lr +#endif addruart r3, r1 mov r1, r0 mov r0, #0 |