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author | Eric Yuen <eyuen@nvidia.com> | 2014-07-08 10:34:33 +0000 |
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committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-07-16 17:22:42 +0200 |
commit | ff09771639a39c834f364a75faa49bc44bac901e (patch) | |
tree | 28a36c5422b02541b6b9be2fc88d73ca88527c61 /arch/arm/mach-bcmring/core.h | |
parent | 491f263ebfb338c59abfbde6d4e0e7256a0150fa (diff) |
arm: tegra3: PCIe Clock and Reset Conform to Specification
PCIe Reset line must be asserted for at least 100us after clock is enabled.
PEX 2 Controller Register fix, offsets are not at constant intervals.
Bug 1521306
Reviewed-on: http://git-master/r/225399
(cherry picked from commit df0760bf515236bed2e87e590509642ab72a01b5)
Change-Id: I7b44ea51e7e02f2bca93cfc75ed85e01ab91fe03
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-bcmring/core.h')
0 files changed, 0 insertions, 0 deletions