diff options
| author | Changhwan Youn <chaos.youn@samsung.com> | 2011-07-16 10:49:41 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-07-20 23:28:12 +0900 |
| commit | 69644a8e23ab66c1a758ebab04cc3cf62d7b5bdd (patch) | |
| tree | afd00a815171ce160ebd9c52056f9179ae274dad /arch/arm/mach-exynos4/cpu.c | |
| parent | eb13f2bf7254f868486179b75d41c8b17a134996 (diff) | |
ARM: EXYNOS4: modify interrupt mappings for external GIC
To support external GIC needs to update mapping of interrupt number.
This patch modifies it for external GIC and accordingly removes
the unused code.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos4/cpu.c')
| -rw-r--r-- | arch/arm/mach-exynos4/cpu.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 91fc9fc8d763..1aaad56ca7e7 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -168,14 +168,6 @@ void __init exynos4_init_irq(void) for (irq = 0; irq < MAX_COMBINER_NR; irq++) { - /* - * From SPI(0) to SPI(39) and SPI(51), SPI(53) are - * connected to the interrupt combiner. These irqs - * should be initialized to support cascade interrupt. - */ - if ((irq >= 40) && !(irq == 51) && !(irq == 53)) - continue; - combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), COMBINER_IRQ(irq, 0)); combiner_cascade_irq(irq, IRQ_SPI(irq)); |