diff options
| author | Anson Huang <b20788@freescale.com> | 2014-10-09 18:04:39 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-04-14 14:00:50 -0500 |
| commit | efc1edf165f6801f479cdb245a2b2391162123bc (patch) | |
| tree | 9f4ffe8750d87361f4b9070117cd7c5096ac95f4 /arch/arm/mach-imx/clk-imx6q.c | |
| parent | c4902fd019aecf9aee18087d607626938a7c5baf (diff) | |
MLK-9669-2 arm: imx: fix the clock warning printed during ddr frequency change procedure.
Recent checks added to the clock code prints warning during ddr frequency change procedure.
Hence the clock rates printed by clk_summary after ddr freq change are incorrect.
This patch fixes the issue by:
1. Removing CLK_SET_RATE_GATE for ocram_clk since it has a busy bit to be checked when
the ocram_podf is changed.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index c4462f9f99dc..e6d5dbba4215 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -92,6 +92,7 @@ static unsigned int const clks_init_on[] __initconst = { IMX6QDL_CLK_MMDC_CH0_AXI, IMX6QDL_CLK_ROM, IMX6QDL_CLK_ARM, + IMX6QDL_CLK_OCRAM, }; static struct clk_div_table clk_enet_ref_table[] = { @@ -432,7 +433,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); else clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); - clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); + clk[IMX6QDL_CLK_OCRAM] = imx_clk_busy_gate("ocram", "ahb", base + 0x74, 28); clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); |