diff options
| author | Anson Huang <Anson.Huang@freescale.com> | 2015-12-16 21:54:50 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | cf4503d18b50123e9ac32ab2e21a279ed04606eb (patch) | |
| tree | 50c4bc80e0266eba1d430e2836cea5aab41267e0 /arch/arm/mach-imx/common.h | |
| parent | 46ecab49c7cca82949ee5b495a68b91af42e5709 (diff) | |
MLK-12025 ARM: imx: M4 should be in RUN mode when resume from DSM
On i.MX7D, only when M4 enters STOP mode, system is able to enter DSM
mode where M4 power will be gated off. This is done by checking
a variable which records M4's power mode. However, when system
resume from DSM, M4 is re-enabled to RUN mode by A7, but the variable
is NOT updated accordingly, so next time system suspend, even
M4 is NOT in STOP mode, system can enter DSM mode, which is
unexpected and would cause bus-freq use count mismatch.
Fix this issue by reset M4 power mode to RUN mode when resume
from DSM.
Signed-off-by: Anson Huang <Anson.Huang@freescale.com>
(cherry picked from commit d22127a8f395edaf719a5bf4874cf22c5bdc8661)
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/common.h')
| -rw-r--r-- | arch/arm/mach-imx/common.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 082633b784ff..f76d3f31bab0 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -81,6 +81,7 @@ void mcc_receive_from_mu_buffer(unsigned int index, unsigned int *data); void mcc_send_via_mu_buffer(unsigned int index, unsigned int data); bool imx_mu_is_m4_in_low_freq(void); bool imx_mu_is_m4_in_stop(void); +void imx_mu_set_m4_run_mode(void); int imx_mu_lpm_ready(bool ready); enum mxc_cpu_pwr_mode { |