diff options
| author | Anson Huang <b20788@freescale.com> | 2015-06-03 22:54:38 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:23:42 -0500 |
| commit | 7ca28f8bde7d5bc0616ec7816622114e2621e59e (patch) | |
| tree | d004674836aeda3b642ba014926b2150bc9a48df /arch/arm/mach-imx/ddr3_freq_imx6.S | |
| parent | bf2ba739b11adab2b8f0c3b10146520a7af7fb6d (diff) | |
MLK-10945 ARM: imx: correct busfreq flow for i.mx6qp/dq/dl
When busfreq transit to low bus mode and back to normal
mode, the delay line settings should be restored, but the
software flow is entering the med setpoint path which is
NOT supported now, it will lead to incorrect delay line
settings for normal mode when busfreq is ever switching
to other mode and back to normal mode;
Store MMDC1 ODT setting as well and improve those MMDC
settings to align with ddr script in uboot, recommended
by design team.
During DLL On/Off switch, pre-charge command should be
only issued to those open banks, otherwise, some boards
busfreq stress test will be failed.
Signed-off-by: Anson Huang <b20788@freescale.com>
Conflicts:
arch/arm/mach-imx/busfreq_ddr3.c
Diffstat (limited to 'arch/arm/mach-imx/ddr3_freq_imx6.S')
| -rw-r--r-- | arch/arm/mach-imx/ddr3_freq_imx6.S | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-imx/ddr3_freq_imx6.S b/arch/arm/mach-imx/ddr3_freq_imx6.S index 66de5ea60c61..888e7c7b2238 100644 --- a/arch/arm/mach-imx/ddr3_freq_imx6.S +++ b/arch/arm/mach-imx/ddr3_freq_imx6.S @@ -509,9 +509,9 @@ poll_conreq_set_1: cmp r0, #(0x4 << 12) bne poll_conreq_set_1 - ldr r0, =0x00008010 + ldr r0, =0x00008050 str r0, [r5, #MMDC0_MDSCR] - ldr r0, =0x00008018 + ldr r0, =0x00008058 str r0, [r5, #MMDC0_MDSCR] /* @@ -635,7 +635,7 @@ cont_1: orr r0, r0, #0x4 str r0, [r5, #MMDC0_MDCF1] - ldr r0, =0x00091680 + ldr r0, =0x00011680 str r0, [r5, #MMDC0_MDMISC] /* enable dqs pull down in the IOMUX. */ @@ -824,14 +824,14 @@ update_iomux1: add r8, r8, #8 /* update MISC register: WALAT, RALAT */ - ldr r0, =0x00081740 + ldr r0, =0x00001740 str r0, [r5, #MMDC0_MDMISC] /* configure ddr devices to dll on, odt. */ - ldr r0, =0x00028031 + ldr r0, =0x00048031 str r0, [r5, #MMDC0_MDSCR] - ldr r0, =0x00028039 + ldr r0, =0x00048039 str r0, [r5, #MMDC0_MDSCR] /* delay for while. */ @@ -848,10 +848,10 @@ cont7: bgt delay7 /* reset dll. */ - ldr r0, =0x09208030 + ldr r0, =0x09408030 str r0, [r5, #MMDC0_MDSCR] - ldr r0, =0x09208038 + ldr r0, =0x09408038 str r0, [r5, #MMDC0_MDSCR] /* delay for while. */ @@ -907,7 +907,7 @@ cont8: add r8, r8, #8 ldr r2, =0x4818 - str r0, [r5, r2] + str r3, [r5, r2] /* delay for while. */ ldr r1, =40 |