diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-01-25 22:16:48 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:20 +0800 |
| commit | 177f7b7bae9d998f9bbb0f2b0b0402c349a70588 (patch) | |
| tree | 6cd710beea69ed08cf8ae8e333e1b527d5464d3b /arch/arm/mach-imx/ddr3_freq_imx7d.S | |
| parent | 2ab673b70fc6f28c35fbe3400c87e7ab0a3cb8ae (diff) | |
MLK-12262-1 ARM: imx: enable ddr auto self-refresh for i.MX7D
Enable DDR auto self-refresh for i.MX7D, when doing DDR
frequency scale or suspend/resume, DDR self-refresh will
be disabled, this is incorrect for saving power, enable it
for all these scenarios.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/ddr3_freq_imx7d.S')
| -rw-r--r-- | arch/arm/mach-imx/ddr3_freq_imx7d.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/ddr3_freq_imx7d.S b/arch/arm/mach-imx/ddr3_freq_imx7d.S index 7e4b49dc2bf6..8aa219fb1bd6 100644 --- a/arch/arm/mach-imx/ddr3_freq_imx7d.S +++ b/arch/arm/mach-imx/ddr3_freq_imx7d.S @@ -237,6 +237,11 @@ ldr r7, =0x0 str r7, [r4, #DDRC_DBG1] + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + .endm .macro switch_to_533m @@ -433,6 +438,11 @@ ldr r7, =0x0 str r7, [r4, #DDRC_DBG1] + /* enable auto self-refresh */ + ldr r7, [r4, #DDRC_PWRCTL] + orr r7, r7, #(1 << 0) + str r7, [r4, #DDRC_PWRCTL] + .endm ENTRY(imx7d_ddr3_freq_change) |