diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2015-12-28 22:38:26 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 3ea7c9eb34f673b538d81527c12f267de6f3ea3b (patch) | |
| tree | ac425b793253ae4047e7a219de4b006b64f90016 /arch/arm/mach-imx/gpcv2.c | |
| parent | d485c47a5235d7b39dfce513e5e9ee1d4d0e24b7 (diff) | |
MLK-12088 ARM: imx: low power idle support for imx7d single core
When only single core online for i.MX7D, the secondary core wfi
flag should be set to make sure low power idle can be entered when
last core enters wfi. Otherwise, DDR/CCM/ANATOP will NOT enter
low power mode as the secondary core wfi flag is always clear;
Make sure the last power up slot do the ack for single core case.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/gpcv2.c')
| -rw-r--r-- | arch/arm/mach-imx/gpcv2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index af1a57afb356..8fdb5ce80abd 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -385,9 +385,9 @@ void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn) imx_gpcv2_set_slot_ack(1, CORE1_A7, false, false); imx_gpcv2_set_slot_ack(2, SCU_A7, false, true); imx_gpcv2_set_slot_ack(6, SCU_A7, true, false); - imx_gpcv2_set_slot_ack(7, CORE0_A7, true, false); if (num_online_cpus() > 1) - imx_gpcv2_set_slot_ack(8, CORE1_A7, true, true); + imx_gpcv2_set_slot_ack(7, CORE1_A7, true, false); + imx_gpcv2_set_slot_ack(8, CORE0_A7, true, true); } else { writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 0 * 0x4); writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 1 * 0x4); |