diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-05-05 18:21:10 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 70ee71e53dbbbaa582b2cdef29e4bfae2aabc80f (patch) | |
| tree | 908590962b06f47e3715ede7302c50f88994d14f /arch/arm/mach-imx/gpcv2.c | |
| parent | e364b37680b87b4199b42f6ba5bcac7a6d9282bc (diff) | |
MLK-12761 ARM: imx: add mu as wakeup source for i.mx7d
When A7 platform is in low power mode while M4 is NOT,
M4 should be able to send message to wake up A7, so
MU must be always as wake up source.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/gpcv2.c')
| -rw-r--r-- | arch/arm/mach-imx/gpcv2.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index 39bfbd41fa04..c9fc9a89394d 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -117,6 +117,23 @@ static u32 gpcv2_mf_request_on[IMR_NUM]; static DEFINE_SPINLOCK(gpcv2_lock); static struct notifier_block nb_mipi, nb_pcie; +void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable) +{ + unsigned int idx = hwirq / 32; + unsigned long flags; + u32 mask; + + /* Sanity check for SPI irq */ + if (hwirq < 32) + return; + + mask = 1 << hwirq % 32; + spin_lock_irqsave(&gpcv2_lock, flags); + gpcv2_wake_irqs[idx] = enable ? gpcv2_wake_irqs[idx] | mask : + gpcv2_wake_irqs[idx] & ~mask; + spin_unlock_irqrestore(&gpcv2_lock, flags); +} + static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) { unsigned int idx = d->hwirq / 32; |