diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-01-26 15:53:28 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2016-01-28 18:54:29 +0800 |
| commit | 141b611ed0aebba426e0fc0baaedaca463a700dc (patch) | |
| tree | f3c96bd1122b9131d7a6e365817edc54253facb8 /arch/arm/mach-imx/gpcv2.c | |
| parent | 67785980f9df193fca36de91b6a008d5f2660394 (diff) | |
MLK-12262-6 ARM: imx: enable memory power down for i.MX7D TO1.1
Enable memory power down for i.MX7D TO1.1 to save power, TO1.0
has issue of entering DSM by mistake, so it is disabled as a
solution, now that this issue is fixed on TO1.1, enable it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/gpcv2.c')
| -rw-r--r-- | arch/arm/mach-imx/gpcv2.c | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index 47afbee43089..d52578d6a1e1 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -606,10 +606,12 @@ void imx_gpcv2_post_resume(void) val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; writel_relaxed(val, gpc_base + GPC_SLPCR); - /* disable memory low power mode */ - val = readl_relaxed(gpc_base + GPC_MLPCR); - val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; - writel_relaxed(val, gpc_base + GPC_MLPCR); + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } for (i = 0; i < IMR_NUM; i++) writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4); @@ -861,10 +863,12 @@ static int __init imx_gpcv2_init(struct device_node *node, val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE; writel_relaxed(val, gpc_base + GPC_SLPCR); - /* disable memory low power mode */ - val = readl_relaxed(gpc_base + GPC_MLPCR); - val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; - writel_relaxed(val, gpc_base + GPC_MLPCR); + if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + /* disable memory low power mode */ + val = readl_relaxed(gpc_base + GPC_MLPCR); + val |= BM_GPC_MLPCR_MEMLP_CTL_DIS; + writel_relaxed(val, gpc_base + GPC_MLPCR); + } /* disable RBC */ imx_gpcv2_enable_rbc(false); |