diff options
author | Anson Huang <b20788@freescale.com> | 2015-08-25 00:24:20 +0800 |
---|---|---|
committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 10:59:55 -0600 |
commit | f0b210a1907bbb65b75e8e9b79fc8f5176cd4305 (patch) | |
tree | 6943f3ca4899f1cafa596a597cd651acc0556f23 /arch/arm/mach-imx/gpcv2.c | |
parent | 215038002cd46472a424bf71b8971bdedd49c80a (diff) |
MLK-11401-1 ARM: imx: correct mipi PGC power up/down flow
For SW power up/down mipi phy in GPC, below flow should
be executed:
1. map mipi phy to A7 domain;
2. enable mipi phy PGC bit if it is a disable operation;
3. do software power up/down request in GPC;
4. wait for the software request bit clear.
Previous flow is incorrect, as it miss #4 step, correct it.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 707ed61de83e7cc1c7d7b15cc8a1c00bea0bc8d1)
Conflicts:
arch/arm/mach-imx/gpcv2.c
Diffstat (limited to 'arch/arm/mach-imx/gpcv2.c')
-rw-r--r-- | arch/arm/mach-imx/gpcv2.c | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index cebfc271f7bc..b55208850155 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -584,28 +584,32 @@ static int imx_mipi_regulator_notify(struct notifier_block *nb, { u32 val = 0; + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val | BIT(2), gpc_base + GPC_PGC_CPU_MAPPING); + switch (event) { case REGULATOR_EVENT_PRE_DO_ENABLE: - val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); - writel_relaxed(val | BIT(2), gpc_base + GPC_PGC_CPU_MAPPING); - val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ); writel_relaxed(val | BIT(0), gpc_base + GPC_PU_PGC_SW_PUP_REQ); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PUP_REQ) & BIT(0)) + ; break; case REGULATOR_EVENT_PRE_DO_DISABLE: + /* only disable phy need to set PGC bit, enable does NOT need */ + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_MIPI_PHY); val = readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ); writel_relaxed(val | BIT(0), gpc_base + GPC_PU_PGC_SW_PDN_REQ); - - val = readl_relaxed(gpc_base + GPC_PGC_MIPI_PHY); - writel_relaxed(val | BIT(0), gpc_base + GPC_PGC_MIPI_PHY); - - val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); - writel_relaxed(val & ~BIT(2), gpc_base + GPC_PGC_CPU_MAPPING); + while (readl_relaxed(gpc_base + GPC_PU_PGC_SW_PDN_REQ) & BIT(0)) + ; + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_MIPI_PHY); break; default: break; } + val = readl_relaxed(gpc_base + GPC_PGC_CPU_MAPPING); + writel_relaxed(val & ~BIT(2), gpc_base + GPC_PGC_CPU_MAPPING); + return NOTIFY_OK; } |