MLK-9955-10 arm: imx: add A9-M4 power management

this patch adds A9-M4 power management, including
below features:

1. busfreq: M4 is registered as a high speed device
   of A9, when M4 is running at high speed, busfreq
   will NOT enter low bus mode, when M4 is entering
   its low power idle, A9 will be able to enter low
   bus mode according to its state machine;
2. low power idle: only when M4 is in its low power
   idle, busfreq is staying at low bus mode, low
   power idle is available for kernel;
3. suspend: when M4 is NOT in its low power idle,
   when linux is about to suspend, it will only
   force SOC enter WAIT mode, only when M4 is in
   its low power idle in TCM, linux suspend can
   enter DSM mode. M4 can request/release wakeup
   source via MU to A9.

as M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:

M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
   power idle;
4. receive interrupt to exit low power idle, send request
   to A9 for increase busfreq and M4 freq, enter wfi
   and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.

A9:
1. when receive M4's message of entering low power idle,
   wait M4 into wfi, hold M4 in wfi by hardware, gate
   M4 clk, then switch M4's clk to OSC, ungate M4 clk,
   send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
   wait M4 into wfi, hold M4 in wfi by hardware, gate
   M4 clk, then switch M4's clk to origin high clk,
   ungate M4 clk, send ready command to wake up M4
   to exit low power idle;

Signed-off-by: Anson Huang <b20788@freescale.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/mx6.h b/arch/arm/mach-imx/mx6.h
index b4bfc28369bd..5f693c33baa0 100644
--- a/arch/arm/mach-imx/mx6.h
+++ b/arch/arm/mach-imx/mx6.h
@@ -26,6 +26,8 @@
 #define MX6Q_ANATOP_SIZE        0x1000
 #define MX6Q_GPC_BASE_ADDR      0x020dc000
 #define MX6Q_GPC_SIZE           0x4000
+#define MX6Q_SEMA4_BASE_ADDR	0x02290000
+#define MX6Q_SEMA4_SIZE		0x4000
 #define MX6Q_MMDC_P0_BASE_ADDR  0x021b0000
 #define MX6Q_MMDC_P0_SIZE       0x4000
 #define MX6Q_MMDC_P1_BASE_ADDR  0x021b4000
@@ -34,6 +36,8 @@
 #define MX6Q_AIPS1_SIZE     0x100000
 #define MX6Q_AIPS2_BASE_ADDR        0x02100000
 #define MX6Q_AIPS2_SIZE     0x100000
+#define MX6Q_AIPS3_BASE_ADDR	0x02200000
+#define MX6Q_AIPS3_SIZE		0x100000
 
 #define MX6SX_IRAM_TLB_BASE_ADDR    0x008f8000
 #define MX6Q_IRAM_TLB_BASE_ADDR 0x00900000