MLK-10455-3 ARM: imx: add different DDR type support for imx7d retention

On i.MX7D, LPDDR3 and DDR3 have different retention flow, need to add DDR
type check during initialization.

Some DDR configurations may be updated lated, so it is better to
just read it from register instead of hard coding.

Signed-off-by: Anson Huang <b20788@freescale.com>

1 files changed, 54 insertions, 43 deletions

diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c
index 6ea2e0ee7512..1d7f28182498 100644
--- a/arch/arm/mach-imx/pm-imx7.c
+++ b/arch/arm/mach-imx/pm-imx7.c
@@ -43,6 +43,7 @@
 #define MX7_MAX_DDRC_PHY_NUM		16
 
 #define MX7_SUSPEND_IRAM_ADDR_OFFSET	0
+#define READ_DATA_FROM_HARDWARE		0
 
 #define UART_UCR1	0x80
 #define UART_UCR2	0x84
@@ -97,46 +98,46 @@ struct imx7_pm_socdata {
 	const u32 (*ddrc_phy_offset)[2];
 };
 
-static const u32 imx7d_ddrc_reg_setting[][2] __initconst = {
-	{ 0x0, 0x03040008 },
-	{ 0x1a0, 0x80400003 },
-	{ 0x1a4, 0x00100020 },
-	{ 0x1a8, 0x80100004 },
-	{ 0x64, 0x00200038 },
+static const u32 imx7d_ddrc_lpddr3_setting[][2] __initconst = {
+	{ 0x0, READ_DATA_FROM_HARDWARE },
+	{ 0x1a0, READ_DATA_FROM_HARDWARE },
+	{ 0x1a4, READ_DATA_FROM_HARDWARE },
+	{ 0x1a8, READ_DATA_FROM_HARDWARE },
+	{ 0x64, READ_DATA_FROM_HARDWARE },
 	{ 0xd0, 0xc0350001 },
-	{ 0xdc, 0x00c3000a },
-	{ 0xe0, 0x00010000 },
-	{ 0xe4, 0x00110006 },
-	{ 0xf4, 0x0000033f },
-	{ 0x100, 0x0a0e110b },
-	{ 0x104, 0x00020211 },
-	{ 0x108, 0x03060707 },
-	{ 0x10c, 0x00a0500c },
-	{ 0x110, 0x05020307 },
-	{ 0x114, 0x02020404 },
-	{ 0x118, 0x02020003 },
-	{ 0x11c, 0x00000202 },
-	{ 0x180, 0x00600018 },
-	{ 0x184, 0x00e00100 },
-	{ 0x190, 0x02098205 },
-	{ 0x194, 0x00060303 },
-	{ 0x200, 0x00000016 },
-	{ 0x204, 0x00171717 },
-	{ 0x214, 0x05050505 },
-	{ 0x218, 0x0f0f0505 },
+	{ 0xdc, READ_DATA_FROM_HARDWARE },
+	{ 0xe0, READ_DATA_FROM_HARDWARE },
+	{ 0xe4, READ_DATA_FROM_HARDWARE },
+	{ 0xf4, READ_DATA_FROM_HARDWARE },
+	{ 0x100, READ_DATA_FROM_HARDWARE },
+	{ 0x104, READ_DATA_FROM_HARDWARE },
+	{ 0x108, READ_DATA_FROM_HARDWARE },
+	{ 0x10c, READ_DATA_FROM_HARDWARE },
+	{ 0x110, READ_DATA_FROM_HARDWARE },
+	{ 0x114, READ_DATA_FROM_HARDWARE },
+	{ 0x118, READ_DATA_FROM_HARDWARE },
+	{ 0x11c, READ_DATA_FROM_HARDWARE },
+	{ 0x180, READ_DATA_FROM_HARDWARE },
+	{ 0x184, READ_DATA_FROM_HARDWARE },
+	{ 0x190, READ_DATA_FROM_HARDWARE },
+	{ 0x194, READ_DATA_FROM_HARDWARE },
+	{ 0x200, READ_DATA_FROM_HARDWARE },
+	{ 0x204, READ_DATA_FROM_HARDWARE },
+	{ 0x214, READ_DATA_FROM_HARDWARE },
+	{ 0x218, READ_DATA_FROM_HARDWARE },
 	{ 0x240, 0x06000601 },
-	{ 0x244, 0x00000000 },
+	{ 0x244, READ_DATA_FROM_HARDWARE },
 };
 
-static const u32 imx7d_ddrc_phy_reg_setting[][2] __initconst = {
-	{ 0x0, 0x17421e40 },
-	{ 0x4, 0x10210100 },
-	{ 0x8, 0x00010000 },
-	{ 0x10, 0x0007080c },
-	{ 0x1c, 0x01010000 },
-	{ 0x9c, 0x00000d6e },
-	{ 0x20, 0x0a0c0a0a },
-	{ 0x30, 0x06060606 },
+static const u32 imx7d_ddrc_phy_lpddr3_setting[][2] __initconst = {
+	{ 0x0, READ_DATA_FROM_HARDWARE },
+	{ 0x4, READ_DATA_FROM_HARDWARE },
+	{ 0x8, READ_DATA_FROM_HARDWARE },
+	{ 0x10, READ_DATA_FROM_HARDWARE },
+	{ 0x1c, READ_DATA_FROM_HARDWARE },
+	{ 0x9c, READ_DATA_FROM_HARDWARE },
+	{ 0x20, READ_DATA_FROM_HARDWARE },
+	{ 0x30, READ_DATA_FROM_HARDWARE },
 	{ 0x50, 0x01000008 },
 	{ 0x50, 0x00000008 },
 	{ 0xc0, 0x0e407304 },
@@ -152,10 +153,10 @@ static const struct imx7_pm_socdata imx7d_pm_data __initconst = {
 	.src_compat = "fsl,imx7d-src",
 	.iomuxc_compat = "fsl,imx7d-iomuxc",
 	.gpc_compat = "fsl,imx7d-gpc",
-	.ddrc_num = ARRAY_SIZE(imx7d_ddrc_reg_setting),
-	.ddrc_offset = imx7d_ddrc_reg_setting,
-	.ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_reg_setting),
-	.ddrc_phy_offset = imx7d_ddrc_phy_reg_setting,
+	.ddrc_num = ARRAY_SIZE(imx7d_ddrc_lpddr3_setting),
+	.ddrc_offset = imx7d_ddrc_lpddr3_setting,
+	.ddrc_phy_num = ARRAY_SIZE(imx7d_ddrc_phy_lpddr3_setting),
+	.ddrc_phy_offset = imx7d_ddrc_phy_lpddr3_setting,
 };
 
 /*
@@ -481,15 +482,25 @@ static int __init imx7_suspend_init(const struct imx7_pm_socdata *socdata)
 	/* initialize DDRC settings */
 	for (i = 0; i < pm_info->ddrc_num; i++) {
 		pm_info->ddrc_val[i][0] = ddrc_offset_array[i][0];
-		pm_info->ddrc_val[i][1] = ddrc_offset_array[i][1];
+		if (ddrc_offset_array[i][1] == READ_DATA_FROM_HARDWARE)
+			pm_info->ddrc_val[i][1] =
+				readl_relaxed(pm_info->ddrc_base.vbase +
+				ddrc_offset_array[i][0]);
+		else
+			pm_info->ddrc_val[i][1] = ddrc_offset_array[i][1];
 	}
 
 	/* initialize DDRC PHY settings */
 	for (i = 0; i < pm_info->ddrc_phy_num; i++) {
 		pm_info->ddrc_phy_val[i][0] =
 			ddrc_phy_offset_array[i][0];
-		pm_info->ddrc_phy_val[i][1] =
-			ddrc_phy_offset_array[i][1];
+		if (ddrc_phy_offset_array[i][1] == READ_DATA_FROM_HARDWARE)
+			pm_info->ddrc_phy_val[i][1] =
+				readl_relaxed(pm_info->ddrc_phy_base.vbase +
+				ddrc_phy_offset_array[i][0]);
+		else
+			pm_info->ddrc_phy_val[i][1] =
+				ddrc_phy_offset_array[i][1];
 	}
 
 	imx7_suspend_in_ocram_fn = fncpy(