diff options
author | Bai Ping <ping.bai@nxp.com> | 2017-03-10 14:54:01 +0800 |
---|---|---|
committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
commit | 7b864ac37259d456a6eafee4208f7b0d86fca5b5 (patch) | |
tree | 1550cfa229d382389d93d3cf64ffda4cff6c7ae8 /arch/arm/mach-imx | |
parent | 190dcca38c704ffa6521cf8b6e5ab56a344c66ae (diff) |
MLK-14409-01 ARM: imx: Add speed grading fuse check for 900MHz on i.mx6ull
According to the latest datasheet(Rev.1,02/2017), when the internal LDO
is enabled, the ARM core can run at 900MHz. We need to check the
speed grading fuse to determine the max ARM core frequency.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/mach-imx6ul.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index bcdcf7e3b12a..851034d5f73f 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -72,7 +72,7 @@ static void __init imx6ul_enet_phy_init(void) #define OCOTP_CFG3 0x440 #define OCOTP_CFG3_SPEED_SHIFT 16 #define OCOTP_CFG3_SPEED_696MHZ 0x2 -#define OCOTP_CFG3_SPEED_1_GHZ 0x3 +#define OCOTP_CFG3_SPEED_900MHZ 0x3 static void __init imx6ul_opp_check_speed_grading(struct device *cpu_dev) { @@ -101,7 +101,7 @@ static void __init imx6ul_opp_check_speed_grading(struct device *cpu_dev) * 2b'00: Reserved; * 2b'01: 528000000Hz; * 2b'10: 700000000Hz(i.MX6UL), 800000000Hz(i.MX6ULL); - * 2b'11: Reserved(i.MX6UL), 1GHz(i.MX6ULL); + * 2b'11: 900000000Hz(i.MX6ULL); * We need to set the max speed of ARM according to fuse map. */ val = readl_relaxed(base + OCOTP_CFG3); @@ -115,15 +115,15 @@ static void __init imx6ul_opp_check_speed_grading(struct device *cpu_dev) } if (cpu_is_imx6ull()) { - if (val != OCOTP_CFG3_SPEED_1_GHZ) { - if (dev_pm_opp_disable(cpu_dev, 996000000)) - pr_warn("Failed to disable 996MHz OPP\n"); - } - if (val != OCOTP_CFG3_SPEED_696MHZ) { if (dev_pm_opp_disable(cpu_dev, 792000000)) pr_warn("Failed to disable 792MHz OPP\n"); } + + if (val != OCOTP_CFG3_SPEED_900MHZ) { + if(dev_pm_opp_disable(cpu_dev, 900000000)) + pr_warn("Failed to disable 900MHz OPP\n"); + } } iounmap(base); |