MLK-16266-02 ARM: imx: Enhance the code to support new TO for imx6qp

Previous code don't take care about the i.MX6QP revision update of
new TO. So improve the code to include future TO support for i.MX6QP.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

4 files changed, 12 insertions, 10 deletions

diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 2470e1a4fead..d46f68417bbb 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -146,7 +146,7 @@ void imx_anatop_pre_suspend(void)
 		return;
 	}
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx_anatop_disable_pu(true);
 
 	if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
@@ -176,7 +176,7 @@ void imx_anatop_post_resume(void)
 		return;
 	}
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx_anatop_disable_pu(false);
 
 	if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 3a28b16936f4..a02b47a0be36 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -126,7 +126,7 @@ struct device * __init imx_soc_device_init(void)
 		soc_id = "i.MX6SX";
 		break;
 	case MXC_CPU_IMX6Q:
-		if (imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+		if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 			soc_id = "i.MX6QP";
 		else
 			soc_id = "i.MX6Q";
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 1629608899a9..551ecd0f2a4f 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -1,6 +1,7 @@
 /*
  * Copyright 2011-2016 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
+ * Copyright 2017 NXP.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -231,7 +232,7 @@ void imx_gpc_pre_suspend(bool arm_power_off)
 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
 	int i;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
 
 	/* power down the mega-fast power domain */
@@ -254,7 +255,7 @@ void imx_gpc_post_resume(void)
 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
 	int i;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		_imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
 
 	/* Keep ARM core powered on for other low-power modes */
@@ -648,7 +649,7 @@ static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
 	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
 
 	if (&imx6q_pu_domain == pu && pu_on && cpu_is_imx6q() &&
-		imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+		imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		return 0;
 
 	_imx6q_pm_pu_power_off(genpd);
@@ -693,7 +694,7 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
 	struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
 	int ret;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0
 		&& &imx6q_pu_domain == pu) {
 		if (!pu_on)
 			pu_on = true;
@@ -856,7 +857,7 @@ static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
 
 	is_off = IS_ENABLED(CONFIG_PM);
 	if (is_off && !(cpu_is_imx6q() &&
-		imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)) {
+		imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)) {
 		_imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
 	} else {
 		/*
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index b884209edaa6..7b2462f7f598 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -1,6 +1,7 @@
 /*
  * Copyright 2011-2015 Freescale Semiconductor, Inc.
  * Copyright 2011 Linaro Ltd.
+ * Copyright 2017 NXP.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -310,7 +311,7 @@ static inline void imx6q_enet_init(void)
 	imx6_enet_mac_init("fsl,imx6q-fec", "fsl,imx6q-ocotp");
 	imx6q_enet_phy_init();
 	imx6q_1588_init();
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx6q_enet_clk_sel();
 }
 
@@ -318,7 +319,7 @@ static void __init imx6q_init_machine(void)
 {
 	struct device *parent;
 
-	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+	if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
 		imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
 	else
 		imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",