diff options
author | Anson Huang <Anson.Huang@nxp.com> | 2016-10-09 22:31:30 +0800 |
---|---|---|
committer | Robby Cai <robby.cai@nxp.com> | 2016-11-16 15:18:44 +0800 |
commit | d24a24641d8ad3249e95a0491bf5ecd0e5fb79b8 (patch) | |
tree | 47654748205010efdd85ef86a90183dc06df44f9 /arch/arm/mach-imx | |
parent | 65e3e8ddcea64fbdb512a2b66977fda6067ec890 (diff) |
MLK-13303-7 ARM: imx: add gpt timer support for i.mx6sll
Add i.MX6SLL GPT timer support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 44b5e3b1252a5c82f1332a5bf17877558c50cae4)
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/time.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 6d4f8a251577..f5fd58ec4e71 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -322,8 +322,9 @@ static void __init _mxc_timer_init(int irq, tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { tctl_val |= V2_TCTL_CLK_OSC_DIV8; - if (cpu_is_imx6dl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull() || cpu_is_imx7d()) { + if (cpu_is_imx6dl() || cpu_is_imx6sll() || + cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx7d()) { /* 24 / 8 = 3 MHz */ __raw_writel(7 << V2_TPRER_PRE24M, timer_base + MXC_TPRER); @@ -384,6 +385,7 @@ CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt); +CLOCKSOURCE_OF_DECLARE(mx6sll_timer, "fsl,imx6sll-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx6ul_timer, "fsl,imx6ul-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx7d_timer, "fsl,imx7d-gpt", mxc_timer_init_dt); |