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authorLiu Ying <b17645@freescale.com>2010-04-09 13:48:19 -0400
committerAlejandro Gonzalez <alex.gonzalez@digi.com>2010-05-25 11:20:23 +0200
commit583a080e0198fdc8555c3cc72e6c18fea6792f23 (patch)
tree59efdc67a3096ada5a791345f5b0786303a4e2f5 /arch/arm/mach-mx5/mx53_evk_gpio.c
parent746bb4c23ddd13ccd6b254e84c4e84f34dacf441 (diff)
ENGR00122388-1 MX53 MSL:Change for support OV3640 camera
This patch includes IOMUX, clock and regulator change for supporting OV3640 camera. Signed-off-by: Liu Ying <b17645@freescale.com> Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm/mach-mx5/mx53_evk_gpio.c')
-rw-r--r--arch/arm/mach-mx5/mx53_evk_gpio.c68
1 files changed, 61 insertions, 7 deletions
diff --git a/arch/arm/mach-mx5/mx53_evk_gpio.c b/arch/arm/mach-mx5/mx53_evk_gpio.c
index 37c489a3e357..7b1efd1bd50c 100644
--- a/arch/arm/mach-mx5/mx53_evk_gpio.c
+++ b/arch/arm/mach-mx5/mx53_evk_gpio.c
@@ -184,9 +184,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT5,
},
{
- MX53_PIN_CSI0_D5, IOMUX_CONFIG_ALT5,
- },
- {
MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT5,
},
{
@@ -395,6 +392,61 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
(PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW),
},
+ { /* audio and CSI clock out */
+ MX53_PIN_GPIO_0, IOMUX_CONFIG_ALT3,
+ },
+ {
+ MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ {
+ MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ {
+ MX53_PIN_CSI0_D14, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ {
+ MX53_PIN_CSI0_D15, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ {
+ MX53_PIN_CSI0_D16, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ {
+ MX53_PIN_CSI0_D17, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ {
+ MX53_PIN_CSI0_D18, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ {
+ MX53_PIN_CSI0_D19, IOMUX_CONFIG_ALT0,
+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_LOW,
+ },
+ { /* Camera VSYNC */
+ MX53_PIN_CSI0_VSYNC, IOMUX_CONFIG_ALT0,
+ },
+ { /* Camera HSYNC */
+ MX53_PIN_CSI0_MCLK, IOMUX_CONFIG_ALT0,
+ },
+ { /* Camera pixclk */
+ MX53_PIN_CSI0_PIXCLK, IOMUX_CONFIG_ALT0,
+ },
+ { /* Camera low power */
+ MX53_PIN_CSI0_D5, IOMUX_CONFIG_ALT1,
+ },
/* esdhc1 */
{
MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
@@ -552,9 +604,6 @@ static struct mxc_iomux_pin_cfg __initdata mx53_evk_iomux_pins[] = {
{ /* FEC_RST */
MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1,
},
- { /* audio clock out */
- MX53_PIN_GPIO_0, IOMUX_CONFIG_ALT3,
- },
};
static struct mxc_iomux_pin_cfg __initdata mx53_arm2_iomux_pins[] = {
@@ -739,9 +788,14 @@ void __init mx53_evk_io_init(void)
/* LCD related gpio */
/* Camera reset */
+ gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), "gpio4_0");
+ gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 0);
+ gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 1);
/* Camera low power */
-
+ gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23");
+ gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
+ gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
}
/* workaround for ecspi chipselect pin may not keep correct level when idle */