diff options
| author | Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com> | 2009-12-10 14:43:56 -0600 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2010-03-25 14:01:41 -0400 |
| commit | 8bd479a5235226b85f5619b0ba1d9f840b858c6a (patch) | |
| tree | 5771734209da6c8a9297feb24804f2fce7342183 /arch/arm/mach-mx51/clock.c | |
| parent | 4f005a73d670e97d67980e33e30b8f373ae50ae3 (diff) | |
ENGR00119202: Fix DVFS-PER related bugs.
DVFS-PER needs to make sure that the pixel clock divider is an
even integer.
Added support for pixel clock being sourced from an external clock (PLL3)
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx51/clock.c')
| -rw-r--r-- | arch/arm/mach-mx51/clock.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-mx51/clock.c b/arch/arm/mach-mx51/clock.c index 3600b649cdba..5b053fc268e6 100644 --- a/arch/arm/mach-mx51/clock.c +++ b/arch/arm/mach-mx51/clock.c @@ -358,6 +358,18 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); } + /* If auto restart is disabled, restart the PLL and + * wait for it to lock. + */ + reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG); + if (!reg & MXC_PLL_DP_CONFIG_AREN) { + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + reg |= MXC_PLL_DP_CTL_RST; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + } + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) + ; + clk->rate = rate; return 0; } |