diff options
| author | Nancy Chen <Nancy.Chen@freescale.com> | 2012-08-14 09:49:05 -0500 |
|---|---|---|
| committer | Nancy Chen <Nancy.Chen@freescale.com> | 2012-08-14 11:59:07 -0500 |
| commit | 4a711bb18e46d81606b804ed7d3c4f918815223f (patch) | |
| tree | 64c589226935c54b3a34856f1e3526e766128100 /arch/arm/mach-mx6/clock_mx6sl.c | |
| parent | 04b005c30fe9ce65e05c2962526b4ddc88565070 (diff) | |
ENGR00220297 [MX6SL]: Fix AHB clock not correct after kernel boot
1. Fix AHB_CLK is not right after system up. ahb_clk is 49.5MHz
after system up. It should be 132MHz.
2. Remove the voltage changes for VDDSOC_CAP since there are vddarm
voltage changed in CPUFREQ and vddsoc voltage and vddarm voltage
should meet the constraint condition: VDDSOC > VDDARM - 50mV. Therefore
VDDSOC voltage changes will be implemented in CPUFREQ.
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock_mx6sl.c')
| -rwxr-xr-x | arch/arm/mach-mx6/clock_mx6sl.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index 3b2d9e527625..7496882feeb1 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -2908,7 +2908,7 @@ static struct clk lcdif_pix_clk = { .set_rate = _clk_lcdif_pix_set_rate, .round_rate = _clk_epdc_lcdif_pix_round_rate, .get_rate = _clk_lcdif_pix_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static struct clk epdc_pix_clk = { @@ -2923,7 +2923,7 @@ static struct clk epdc_pix_clk = { .set_rate = _clk_epdc_pix_set_rate, .round_rate = _clk_epdc_lcdif_pix_round_rate, .get_rate = _clk_epdc_pix_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_spdif_round_rate(struct clk *clk, unsigned long rate) |