diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-22 13:26:11 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-26 14:57:13 -0500 |
| commit | d3f7f366becf5e31225dbe1aaceef84813f7ccb8 (patch) | |
| tree | b04618dfc6168ea7563cd5d260407fc26df43ec5 /arch/arm/mach-mx6/clock_mx6sl.c | |
| parent | df63a57d034f77674d2fce9949f0eef6570e02f0 (diff) | |
ENGR00221161 [MX6SL]- Add audio bus freq mode support.
Set DDR to 50MHz in low power audio playback.
AHB/AXI are at 24MHz.
Also fix correct usecount for PLL1 main clock. If not
it causes issues when pll1_sw_clk's parent is changed.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock_mx6sl.c')
| -rwxr-xr-x | arch/arm/mach-mx6/clock_mx6sl.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index d93320d59dd8..4839f1542b3a 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -1236,6 +1236,7 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) pll1_sys_main_clk.disable(&pll1_sys_main_clk); pll1_sys_main_clk.usecount = 0; } + spin_unlock_irqrestore(&mx6sl_clk_lock, flags); return 0; @@ -2451,7 +2452,7 @@ static struct clk ssi1_clk = { #else .secondary = &mmdc_ch1_axi_clk[0], #endif - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_ssi2_get_rate(struct clk *clk) @@ -2525,7 +2526,7 @@ static struct clk ssi2_clk = { #else .secondary = &mmdc_ch1_axi_clk[0], #endif - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_ssi3_get_rate(struct clk *clk) @@ -2598,7 +2599,7 @@ static struct clk ssi3_clk = { #else .secondary = &mmdc_ch1_axi_clk[0], #endif - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_AUDIO_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_epdc_lcdif_pix_round_rate(struct clk *clk, |