diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-30 14:45:10 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-31 00:07:58 -0500 |
| commit | 5fd60addbbc2ca8083b15378fa460e41f5d94326 (patch) | |
| tree | 1078cf35cf940b4407ce0263a457b6bd71febd3c /arch/arm/mach-mx6/cpu_op-mx6.c | |
| parent | 4d64e8b36e4eb36ed5ad583f7c17b272ef464d7b (diff) | |
ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE support
Need to ensure that the ARM_CLK rate stays exactly the same
when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system
enters 24MHz state. Also need to ensure that PLL1 is enabled
before relocking the PLL to the correct rate.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/cpu_op-mx6.c')
| -rw-r--r-- | arch/arm/mach-mx6/cpu_op-mx6.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c index 80e1c1089632..7e054c1d743c 100644 --- a/arch/arm/mach-mx6/cpu_op-mx6.c +++ b/arch/arm/mach-mx6/cpu_op-mx6.c @@ -229,6 +229,7 @@ static struct cpu_op mx6sl_cpu_op_1G[] = { .cpu_voltage = 1200000,}, { .pll_rate = 396000000, + .pll_lpm_rate = 792000000, .cpu_rate = 396000000, .cpu_podf = 0, .pu_voltage = 1050000, @@ -236,6 +237,7 @@ static struct cpu_op mx6sl_cpu_op_1G[] = { .cpu_voltage = 1100000,}, { .pll_rate = 396000000, + .pll_lpm_rate = 792000000, .cpu_rate = 198000000, .cpu_podf = 1, .pu_voltage = 1050000, @@ -253,6 +255,7 @@ static struct cpu_op mx6sl_cpu_op[] = { .cpu_voltage = 1200000,}, { .pll_rate = 396000000, + .pll_lpm_rate = 792000000, .cpu_rate = 396000000, .cpu_podf = 0, .pu_voltage = 1050000, @@ -260,6 +263,7 @@ static struct cpu_op mx6sl_cpu_op[] = { .cpu_voltage = 1100000,}, { .pll_rate = 396000000, + .pll_lpm_rate = 792000000, .cpu_rate = 198000000, .cpu_podf = 1, .pu_voltage = 1050000, |