ENGR00174037-1 Add HSIC suspend/resume feature

MSL part

- For HSIC, not connect nor disconnect, then WKCN,
  WKDC must not be set during suspend
- For HSIC, must set bit 21 in host control registry
  after device connected to host controller
- USB PHY 480M clock output must turn on to avoid about
  10ms delay before sending out resume signal
- HW_ANA_MISC clkgate delay must be set to 2 or 3 to
  avoid 24M OSCI not stable issue

Signed-off-by: Tony LIU <junjie.liu@freescale.com>

1 files changed, 24 insertions, 2 deletions

diff --git a/arch/arm/mach-mx6/usb_h3.c b/arch/arm/mach-mx6/usb_h3.c
index 43c2b1208eed..93210b48805a 100644
--- a/arch/arm/mach-mx6/usb_h3.c
+++ b/arch/arm/mach-mx6/usb_h3.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -43,11 +43,17 @@ static struct fsl_usb2_platform_data usbh3_config;
 static void usbh3_internal_phy_clock_gate(bool on)
 {
 	if (on) {
+		/* must turn on the 480M clock, otherwise
+		 * there will be a 10ms delay before host
+		 * controller send out resume signal*/
 		USB_H3_CTRL |= UCTRL_UTMI_ON_CLOCK;
 		USB_UH3_HSIC_CTRL |= HSIC_CLK_ON;
 	} else {
 		USB_UH3_HSIC_CTRL &= ~HSIC_CLK_ON;
-		USB_H3_CTRL &= ~UCTRL_UTMI_ON_CLOCK;
+		/* can't turn off this clock, otherwise
+		 * there will be a 10ms delay before host
+		 * controller send out resume signal*/
+		/*USB_H3_CTRL &= ~UCTRL_UTMI_ON_CLOCK;*/
 	}
 }
 
@@ -114,6 +120,10 @@ void mx6_set_host3_vbus_func(driver_vbus_func driver_vbus)
 static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
 {
 	pr_debug("host3, %s, enable is %d\n", __func__, enable);
+	/* for HSIC, no disconnect nor connect
+	 * we need to disable the WKDS, WKCN */
+	UH3_PORTSC1 &= ~(PORTSC_WKDC | PORTSC_WKCN);
+
 	if (enable) {
 		USB_H3_CTRL |= (UCTRL_OWIE);
 	} else {
@@ -173,6 +183,13 @@ static void hsic_start(void)
 	mxc_iomux_v3_setup_pad(MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START);
 }
 
+static void hsic_device_connected(void)
+{
+	pr_debug("%s\n", __func__);
+	if (!(USB_UH3_HSIC_CTRL & HSIC_DEV_CONN))
+		USB_UH3_HSIC_CTRL |= HSIC_DEV_CONN;
+}
+
 static struct fsl_usb2_platform_data usbh3_config = {
 	.name		= "Host 3",
 	.init		= fsl_usb_host_init_ext,
@@ -187,6 +204,7 @@ static struct fsl_usb2_platform_data usbh3_config = {
 	.wakeup_handler = usbh3_wakeup_handler,
 	.transceiver = "hsic_xcvr",
 	.hsic_post_ops = hsic_start,
+	.hsic_device_connected = hsic_device_connected,
 };
 
 static struct fsl_usb2_wakeup_platform_data usbh3_wakeup_config = {
@@ -213,4 +231,8 @@ void __init mx6_usb_h3_init(void)
 	 */
 	__raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
 			anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_SET);
+	/* must change the clkgate delay to 2 or 3 to avoid
+	 * 24M OSCI clock not stable issue */
+	__raw_writel(BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(3),
+			anatop_base_addr + HW_ANADIG_ANA_MISC0);
 }