diff options
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2010-02-18 08:59:06 +0000 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2010-02-23 10:57:40 -0800 |
| commit | e03d37d85909fd9b09e78087c57b45972a7664ad (patch) | |
| tree | 9c026405e45ee7597eb45c1d596d39952c3888c3 /arch/arm/mach-omap2/serial.c | |
| parent | ae46ec77311b550be992339c1e01fc20bc65296e (diff) | |
omap3/4: uart: fix full-fifo write abort
This patch is addition to the already merged commit on non-empty
uart fifo read abort. "ce13d4716a276f4331d78ba28a5093a63822ab95"
OMAP3630 and OMAP4430 UART IP blocks have a restriction on TX FIFO
too. If you try to write to the tx fifo when it is full, the system aborts.
More details on this thread are here:
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg19447.html
This can be easily reproducible by not suppressing interconnect errors or
long duration testing where continuous prints over console from multiple
threads. This patch is addressing the issue by ensuring that write is
not issued while fifo is full. A timeout is added to avoid any hang
on fifo-full for 10 mS which is unlikely case.
Patch is validated on OMAP3630 and OMAP4 SDP.
V2 version removed the additional 1 uS on every TX as per
Tony's suggestion
Signed-off-by: Woodruff Richard <r-woodruff2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Ghorai Sukumar <s-ghorai@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/serial.c')
| -rw-r--r-- | arch/arm/mach-omap2/serial.c | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 5f3035ec0d6f..b79bc8926cc9 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -23,6 +23,7 @@ #include <linux/serial_reg.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/delay.h> #include <plat/common.h> #include <plat/board.h> @@ -160,6 +161,13 @@ static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, return (unsigned int)__raw_readb(up->membase + offset); } +static inline void __serial_write_reg(struct uart_port *up, int offset, + int value) +{ + offset <<= up->regshift; + __raw_writeb(value, up->membase + offset); +} + static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, int value) { @@ -620,6 +628,20 @@ static unsigned int serial_in_override(struct uart_port *up, int offset) return __serial_read_reg(up, offset); } +static void serial_out_override(struct uart_port *up, int offset, int value) +{ + unsigned int status, tmout = 10000; + + status = __serial_read_reg(up, UART_LSR); + while (!(status & UART_LSR_THRE)) { + /* Wait up to 10ms for the character(s) to be sent. */ + if (--tmout == 0) + break; + udelay(1); + status = __serial_read_reg(up, UART_LSR); + } + __serial_write_reg(up, offset, value); +} void __init omap_serial_early_init(void) { int i; @@ -721,11 +743,14 @@ void __init omap_serial_init_port(int port) * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ - if (cpu_is_omap44xx()) + if (cpu_is_omap44xx()) { uart->p->serial_in = serial_in_override; - else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) + uart->p->serial_out = serial_out_override; + } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) + >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { uart->p->serial_in = serial_in_override; + uart->p->serial_out = serial_out_override; + } } /** |