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authorArnd Hannemann <arnd@arndnet.de>2010-12-28 22:22:33 +0000
committerPaul Mundt <lethal@linux-sh.org>2011-01-12 14:44:19 +0900
commit330e4e7169be3d587dcd7408003197a6f1d66dd0 (patch)
treef0ea7447b65e6355ee985c778d2b523d226e0053 /arch/arm/mach-shmobile
parent4162cf64973df51fc885825bc9ca4d055891c49f (diff)
ARM: mach-shmobile: sh7372 Enable SDIO IRQs
This patch enables the interrupt generation for SDIO IRQs of the sdhi controllers of the SoC. To make sure interrupts are handled announce the MMC_CAP_SDIO_IRQ capability on AP4EVB. Tested with a b43-based SDIO wireless card. Signed-off-by: Arnd Hannemann <arnd@arndnet.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c3
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c4
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index cd79d7c1ba0d..f888d9d1d010 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -308,6 +308,7 @@ static struct platform_device sh_mmcif_device = {
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
+ .tmio_caps = MMC_CAP_SDIO_IRQ,
};
static struct resource sdhi0_resources[] = {
@@ -339,7 +340,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
.tmio_ocr_mask = MMC_VDD_165_195,
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
- .tmio_caps = MMC_CAP_NEEDS_POLL,
+ .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
.get_cd = slot_cn7_get_cd,
};
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 30b2f400666a..f78a1ead71a5 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -230,10 +230,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
0, 0, MSIOF2, 0 } },
{ 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
- { DISABLED, DISABLED, ENABLED, ENABLED,
+ { DISABLED, ENABLED, ENABLED, ENABLED,
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
{ 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
- { 0, DISABLED, ENABLED, ENABLED,
+ { 0, ENABLED, ENABLED, ENABLED,
TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
{ 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
{ CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,