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authorOskar Schirmer <oskar@linutronix.de>2011-02-17 16:43:00 +0100
committerThomas Gleixner <tglx@linutronix.de>2011-03-11 10:06:06 +0100
commit25d7a6003b5c76b735fdfc3dc5030d9d9c93844e (patch)
tree900c037d25bbaf88c0ef57dda0a02cf152142b09 /arch/arm/mach-tcc8k
parentfe03a9f7bb89e920e60fd1bb074adab2eed2bf48 (diff)
arm: tcc8k: Avoid reading clock register twice
There is no reason why in case of PLL2 the configuration register should be read twice, while for PLL0/1 using the value previously read is used. Do the same for PLL2. Signed-off-by: Oskar Schirmer <oskar@linutronix.de> Cc: bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mach-tcc8k')
-rw-r--r--arch/arm/mach-tcc8k/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
index 7ebcbff4652a..a25e3fcb716f 100644
--- a/arch/arm/mach-tcc8k/clock.c
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -199,7 +199,7 @@ static unsigned long get_rate_pll_div(int pll)
addr = CKC_BASE + CLKDIVC1_OFFS;
reg = __raw_readl(addr);
if (reg & CLKDIVC1_P2E)
- div = __raw_readl(addr) & 0x3f;
+ div = reg & 0x3f;
break;
}
return get_rate_pll(pll) / (div + 1);