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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-02-05 13:00:04 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-02-05 13:00:04 +0100 |
| commit | 2fbc9e65c3e248edeb29ff6281658f7c4e1f83ad (patch) | |
| tree | e1751ad7f62aba6ebe738f2d464932d7e17e9f65 /arch/arm/mach-tegra/board-apalis_t30-panel.c | |
| parent | 4281b0f06abbe077d23d4b6f0e078cef95d4c091 (diff) | |
apalis_t30: add LG LP156WF1 display timings
This patch adds display timings for the LG LP156WF1 15.6 inch full HD
dual channel LVDS panel.
Diffstat (limited to 'arch/arm/mach-tegra/board-apalis_t30-panel.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-apalis_t30-panel.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-apalis_t30-panel.c b/arch/arm/mach-tegra/board-apalis_t30-panel.c index 04624110bce3..6d87e20a5397 100644 --- a/arch/arm/mach-tegra/board-apalis_t30-panel.c +++ b/arch/arm/mach-tegra/board-apalis_t30-panel.c @@ -397,6 +397,19 @@ static struct tegra_dc_mode apalis_t30_panel_modes[] = { //high active vertical sync polarity }, { + /* LG LP156WF1 15.6 inch full HD dual channel LVDS panel */ + .pclk = 138500000, + .h_sync_width = 32, + .v_sync_width = 5, + .h_back_porch = 80, + .v_back_porch = 46, + .h_active = 1920, + .v_active = 1080, + .h_front_porch = 48, + .v_front_porch = 6, + //low active sync polarities, high pixel clock polarity + }, + { /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */ .pclk = 148500000, .h_ref_to_sync = 11, |