diff options
| author | Rohit Khanna <rokhanna@nvidia.com> | 2014-05-30 15:18:32 -0700 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2014-06-09 04:05:48 -0700 |
| commit | 394cde6ed4309d815e3a003c0875956eb7275cf8 (patch) | |
| tree | d3319c0e912c5be38ee890165e6053c22b0925f8 /arch/arm/mach-tegra/board-ardbeg-memory.c | |
| parent | 29ec7033c077d15f7c2806280c5d2ece015e2bdd (diff) | |
arm: t132: emc: update dvfs table fr PM359 Laguna
Update DVFS table for PM359 from V1 to V2. The main difference between V2 and V1
is due to the emc_reg_calc update from V6.0.0 to V6.0.4.
- Disable SEL_DPD on MID package
- Increase tR2p by 2 for 102MHz CFG
Bug 1427416
Change-Id: I3199fa8a2118b92bc7f5e8c8cf14c0e0e48d2527
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/417882
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-ardbeg-memory.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-ardbeg-memory.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c index 8d8103c84e2c..f2a5bded1862 100644 --- a/arch/arm/mach-tegra/board-ardbeg-memory.c +++ b/arch/arm/mach-tegra/board-ardbeg-memory.c @@ -3199,8 +3199,8 @@ static struct tegra12_emc_table ardbeg_ddr3_emc_table_pm359[] = { #else static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = { { - 0x19, /* V6.0.0 */ - "01_204000_00_V6.0.0_V1.1", /* DVFS table version */ + 0x19, /* V6.0.4 */ + "02_204000_01_V6.0.4_V1.1", /* DVFS table version */ 204000, /* SDRAM frequency */ 800, /* min voltage */ 800, /* gpu min voltage */ @@ -3216,7 +3216,7 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = { 0x00000002, /* EMC_RP */ 0x00000005, /* EMC_R2W */ 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ + 0x00000005, /* EMC_R2P */ 0x0000000b, /* EMC_W2P */ 0x00000002, /* EMC_RD_RCD */ 0x00000002, /* EMC_WR_RCD */ @@ -3363,14 +3363,14 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = { 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06040203, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0404, /* MC_EMEM_ARB_DA_COVERS */ + 0x000a0504, /* MC_EMEM_ARB_DA_COVERS */ 0x73840a05, /* MC_EMEM_ARB_MISC0 */ 0x70000f03, /* MC_EMEM_ARB_MISC1 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ @@ -3413,7 +3413,7 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x73240000, /* EMC_CFG */ 0x0000088d, /* EMC_CFG_2 */ - 0x00040008, /* EMC_SEL_DPD_CTRL */ + 0x00040000, /* EMC_SEL_DPD_CTRL */ 0x002c0068, /* EMC_CFG_DIG_DLL */ 0x00000008, /* EMC_BGBIAS_CTL0 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ @@ -3426,8 +3426,8 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = { 3420, /* expected dvfs latency (ns) */ }, { - 0x19, /* V6.0.0 */ - "01_732000_00_V6.0.0_V1.1", /* DVFS table version */ + 0x19, /* V6.0.4 */ + "02_732000_01_V6.0.4_V1.1", /* DVFS table version */ 732000, /* SDRAM frequency */ 980, /* min voltage */ 980, /* gpu min voltage */ @@ -3557,7 +3557,7 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = { 0x100002a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ 0x00111111, /* EMC_XM2CMDPADCTRL5 */ - 0x0123133d, /* EMC_XM2DQSPADCTRL2 */ + 0x0121113d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL3 */ 0x77ffc085, /* EMC_XM2CLKPADCTRL */ @@ -3640,7 +3640,7 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x73300000, /* EMC_CFG */ 0x0000089d, /* EMC_CFG_2 */ - 0x00040008, /* EMC_SEL_DPD_CTRL */ + 0x00040000, /* EMC_SEL_DPD_CTRL */ 0xe0090069, /* EMC_CFG_DIG_DLL */ 0x00000000, /* EMC_BGBIAS_CTL0 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ |