arm: T132: emc: updated dvfs table for PM359

DVFS table modified for PM359 to update entry for
204 and removed entry for 102.

Bug 1427416

Change-Id: I033254cdb825cb6cb95679089f152630b4bfb707
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/386465
Reviewed-by: Rohit Khanna <rokhanna@nvidia.com>
Tested-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

1 files changed, 73 insertions, 73 deletions

diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c
index 5d3a976efdaf..bbcaed794b41 100644
--- a/arch/arm/mach-tegra/board-ardbeg-memory.c
+++ b/arch/arm/mach-tegra/board-ardbeg-memory.c
@@ -3200,65 +3200,65 @@ static struct tegra12_emc_table ardbeg_ddr3_emc_table_pm359[] = {
 static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = {
 	{
 		0x19,       /* V6.0.0 */
-		"01_pre_102000_NoCfgVersion_V6.0.0_V1.1", /* DVFS table version */
-		102000,     /* SDRAM frequency */
+		"01_204000_00_V6.0.0_V1.1", /* DVFS table version */
+		204000,     /* SDRAM frequency */
 		800,        /* min voltage */
 		800,        /* gpu min voltage */
 		"pllp_out0", /* clock source id */
-		0x40000006, /* CLK_SOURCE_EMC */
+		0x40000002, /* CLK_SOURCE_EMC */
 		165,        /* number of burst_regs */
 		31,         /* number of up_down_regs */
 		{
-			0x00000004, /* EMC_RC */
-			0x0000001a, /* EMC_RFC */
+			0x00000009, /* EMC_RC */
+			0x00000035, /* EMC_RFC */
 			0x00000000, /* EMC_RFC_SLR */
-			0x00000003, /* EMC_RAS */
-			0x00000001, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
+			0x00000006, /* EMC_RAS */
+			0x00000002, /* EMC_RP */
+			0x00000005, /* EMC_R2W */
 			0x0000000a, /* EMC_W2R */
 			0x00000003, /* EMC_R2P */
 			0x0000000b, /* EMC_W2P */
-			0x00000001, /* EMC_RD_RCD */
-			0x00000001, /* EMC_WR_RCD */
+			0x00000002, /* EMC_RD_RCD */
+			0x00000002, /* EMC_WR_RCD */
 			0x00000003, /* EMC_RRD */
 			0x00000003, /* EMC_REXT */
 			0x00000000, /* EMC_WEXT */
-			0x00000006, /* EMC_WDV */
-			0x00000006, /* EMC_WDV_MASK */
+			0x00000005, /* EMC_WDV */
+			0x00000005, /* EMC_WDV_MASK */
 			0x00000006, /* EMC_QUSE */
 			0x00000002, /* EMC_QUSE_WIDTH */
 			0x00000000, /* EMC_IBDLY */
-			0x00000005, /* EMC_EINPUT */
-			0x00000005, /* EMC_EINPUT_DURATION */
+			0x00000004, /* EMC_EINPUT */
+			0x00000006, /* EMC_EINPUT_DURATION */
 			0x00010000, /* EMC_PUTERM_EXTRA */
 			0x00000003, /* EMC_PUTERM_WIDTH */
 			0x00000000, /* EMC_PUTERM_ADJ */
 			0x00000000, /* EMC_CDB_CNTL_1 */
 			0x00000000, /* EMC_CDB_CNTL_2 */
 			0x00000000, /* EMC_CDB_CNTL_3 */
-			0x00000004, /* EMC_QRST */
-			0x0000000c, /* EMC_QSAFE */
-			0x0000000d, /* EMC_RDV */
-			0x0000000f, /* EMC_RDV_MASK */
-			0x00000304, /* EMC_REFRESH */
+			0x00000003, /* EMC_QRST */
+			0x0000000d, /* EMC_QSAFE */
+			0x0000000f, /* EMC_RDV */
+			0x00000011, /* EMC_RDV_MASK */
+			0x00000607, /* EMC_REFRESH */
 			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x000000c1, /* EMC_PRE_REFRESH_REQ_CNT */
+			0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
 			0x00000002, /* EMC_PDEX2WR */
 			0x00000002, /* EMC_PDEX2RD */
 			0x00000001, /* EMC_PCHG2PDEN */
 			0x00000000, /* EMC_ACT2PDEN */
-			0x00000018, /* EMC_AR2PDEN */
+			0x00000032, /* EMC_AR2PDEN */
 			0x0000000f, /* EMC_RW2PDEN */
-			0x0000001c, /* EMC_TXSR */
-			0x0000001c, /* EMC_TXSRDLL */
+			0x00000038, /* EMC_TXSR */
+			0x00000038, /* EMC_TXSRDLL */
 			0x00000004, /* EMC_TCKE */
 			0x00000005, /* EMC_TCKESR */
 			0x00000004, /* EMC_TPD */
-			0x00000003, /* EMC_TFAW */
+			0x00000007, /* EMC_TFAW */
 			0x00000000, /* EMC_TRPAB */
 			0x00000005, /* EMC_TCLKSTABLE */
 			0x00000005, /* EMC_TCLKSTOP */
-			0x0000031c, /* EMC_TREFBW */
+			0x00000638, /* EMC_TREFBW */
 			0x00000000, /* EMC_FBIO_CFG6 */
 			0x00000000, /* EMC_ODT_WRITE */
 			0x00000000, /* EMC_ODT_READ */
@@ -3291,10 +3291,10 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = {
 			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
 			0x00000000, /* EMC_DLL_XFORM_ADDR0 */
 			0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+			0x00008000, /* EMC_DLL_XFORM_ADDR2 */
 			0x00000000, /* EMC_DLL_XFORM_ADDR3 */
 			0x00000000, /* EMC_DLL_XFORM_ADDR4 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+			0x00008000, /* EMC_DLL_XFORM_ADDR5 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE8 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE9 */
 			0x00000000, /* EMC_DLL_XFORM_QUSE10 */
@@ -3319,14 +3319,14 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = {
 			0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
 			0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ0 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ1 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ2 */
-			0x000fc000, /* EMC_DLL_XFORM_DQ3 */
-			0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
-			0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
-			0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
-			0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+			0x00090000, /* EMC_DLL_XFORM_DQ0 */
+			0x00090000, /* EMC_DLL_XFORM_DQ1 */
+			0x00090000, /* EMC_DLL_XFORM_DQ2 */
+			0x00090000, /* EMC_DLL_XFORM_DQ3 */
+			0x00009000, /* EMC_DLL_XFORM_DQ4 */
+			0x00009000, /* EMC_DLL_XFORM_DQ5 */
+			0x00009000, /* EMC_DLL_XFORM_DQ6 */
+			0x00009000, /* EMC_DLL_XFORM_DQ7 */
 			0x10000280, /* EMC_XM2CMDPADCTRL */
 			0x00000000, /* EMC_XM2CMDPADCTRL4 */
 			0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -3334,7 +3334,7 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = {
 			0x00000000, /* EMC_XM2DQPADCTRL2 */
 			0x00000000, /* EMC_XM2DQPADCTRL3 */
 			0x77ffc081, /* EMC_XM2CLKPADCTRL */
-			0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+			0x00000707, /* EMC_XM2CLKPADCTRL2 */
 			0x81f1f108, /* EMC_XM2COMPPADCTRL */
 			0x07070004, /* EMC_XM2VTTGENPADCTRL */
 			0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
@@ -3344,76 +3344,76 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = {
 			0x00514514, /* EMC_XM2DQSPADCTRL5 */
 			0x51451400, /* EMC_XM2DQSPADCTRL6 */
 			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x00000033, /* EMC_TXDSRVTTGEN */
+			0x00000066, /* EMC_TXDSRVTTGEN */
 			0x00000000, /* EMC_FBIO_SPARE */
-			0x00000000, /* EMC_ZCAL_INTERVAL */
-			0x00000042, /* EMC_ZCAL_WAIT_CNT */
+			0x00020000, /* EMC_ZCAL_INTERVAL */
+			0x00000100, /* EMC_ZCAL_WAIT_CNT */
 			0x000e000e, /* EMC_MRS_WAIT_CNT */
 			0x000e000e, /* EMC_MRS_WAIT_CNT2 */
 			0x00000000, /* EMC_CTT */
 			0x00000003, /* EMC_CTT_DURATION */
-			0x0000f2f3, /* EMC_CFG_PIPE */
-			0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+			0x0000d2b3, /* EMC_CFG_PIPE */
+			0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
 			0x0000000a, /* EMC_QPOP */
-			0x08000001, /* MC_EMEM_ARB_CFG */
-			0x80000026, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+			0x01000003, /* MC_EMEM_ARB_CFG */
+			0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000003, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+			0x00000004, /* MC_EMEM_ARB_TIMING_RC */
+			0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+			0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
 			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
 			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
 			0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
 			0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
 			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
 			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06030203, /* MC_EMEM_ARB_DA_TURNS */
-			0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
-			0x73c30504, /* MC_EMEM_ARB_MISC0 */
+			0x06040203, /* MC_EMEM_ARB_DA_TURNS */
+			0x000a0404, /* MC_EMEM_ARB_DA_COVERS */
+			0x73840a05, /* MC_EMEM_ARB_MISC0 */
 			0x70000f03, /* MC_EMEM_ARB_MISC1 */
 			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
 		},
 		{
 			0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
-			0x00000031, /* MC_PTSA_GRANT_DECREMENT */
-			0x00ff00da, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-			0x00ff00da, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-			0x00ff0075, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-			0x00ff009d, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-			0x00ff009d, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-			0x009b0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+			0x00000062, /* MC_PTSA_GRANT_DECREMENT */
+			0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+			0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+			0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+			0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+			0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+			0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+			0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+			0x004e0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
 			0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
 			0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
 			0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-			0x000800ad, /* MC_LATENCY_ALLOWANCE_HC_0 */
+			0x00080057, /* MC_LATENCY_ALLOWANCE_HC_0 */
 			0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
 			0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-			0x00ff00c6, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-			0x00ff006d, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+			0x00ff0063, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+			0x00ff0036, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
 			0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-			0x00ff00d6, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+			0x00ff006b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
 			0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-			0x0000009f, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+			0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
 			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-			0x0000009f, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+			0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
 			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-			0x009f00a0, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+			0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+			0x00510050, /* MC_LATENCY_ALLOWANCE_VDE_1 */
 			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
 			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-			0x00ff00da, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+			0x00ff00c6, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+			0x00ff006d, /* MC_LATENCY_ALLOWANCE_AFI_0 */
 		},
 		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
 		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
 		0x00000802, /* EMC_CTT_TERM_CTRL */
 		0x73240000, /* EMC_CFG */
-		0x000008c5, /* EMC_CFG_2 */
-		0x00040128, /* EMC_SEL_DPD_CTRL */
+		0x0000088d, /* EMC_CFG_2 */
+		0x00040008, /* EMC_SEL_DPD_CTRL */
 		0x002c0068, /* EMC_CFG_DIG_DLL */
 		0x00000008, /* EMC_BGBIAS_CTL0 */
 		0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
@@ -3423,11 +3423,11 @@ static struct tegra12_emc_table t132_laguna_erss_ddr3_emc_table_pm359[] = {
 		0x80100003, /* Mode Register 1 */
 		0x80200008, /* Mode Register 2 */
 		0x00000000, /* Mode Register 4 */
-		6890,       /* expected dvfs latency (ns) */
+		3420,       /* expected dvfs latency (ns) */
 	},
 	{
 		0x19,       /* V6.0.0 */
-		"01_pre_732000_NoCfgVersion_V6.0.0_V1.1", /* DVFS table version */
+		"01_732000_00_V6.0.0_V1.1", /* DVFS table version */
 		732000,     /* SDRAM frequency */
 		980,        /* min voltage */
 		980,        /* gpu min voltage */