arm: tegra: remove 312Mhz due to memqual failure

Change-Id: Ic1ff0cf3eb9aada54fdf0c803c430439ce598dfc
Signed-off-by: Xue Dong <xdong@nvidia.com>
(cherry picked from commit 714fffcab30ed95018c03df4743de00a9c8a2d61)
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>

1 files changed, 0 insertions, 224 deletions

diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c
index 5e13ee5b7d12..5b48dec8a7ea 100644
--- a/arch/arm/mach-tegra/board-ardbeg-memory.c
+++ b/arch/arm/mach-tegra/board-ardbeg-memory.c
@@ -926,230 +926,6 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
 	},
 	{
 		0x15,       /* V5.0.2 */
-		"04_312000_2_V5.0.2_V0.3", /* DVFS table version */
-		312000,     /* SDRAM frequency */
-		820,        /* min voltage */
-		800,        /* gpu min voltage */
-		"pllm_out0", /* clock source id */
-		0x00000002, /* CLK_SOURCE_EMC */
-		167,        /* number of burst_regs */
-		31,         /* number of up_down_regs */
-		{
-			0x0000000d, /* EMC_RC */
-			0x00000050, /* EMC_RFC */
-			0x00000000, /* EMC_RFC_SLR */
-			0x00000009, /* EMC_RAS */
-			0x00000003, /* EMC_RP */
-			0x00000004, /* EMC_R2W */
-			0x00000008, /* EMC_W2R */
-			0x00000002, /* EMC_R2P */
-			0x00000009, /* EMC_W2P */
-			0x00000003, /* EMC_RD_RCD */
-			0x00000003, /* EMC_WR_RCD */
-			0x00000002, /* EMC_RRD */
-			0x00000002, /* EMC_REXT */
-			0x00000000, /* EMC_WEXT */
-			0x00000003, /* EMC_WDV */
-			0x00000003, /* EMC_WDV_MASK */
-			0x00000005, /* EMC_QUSE */
-			0x00000002, /* EMC_QUSE_WIDTH */
-			0x00000000, /* EMC_IBDLY */
-			0x00000002, /* EMC_EINPUT */
-			0x00000006, /* EMC_EINPUT_DURATION */
-			0x00030000, /* EMC_PUTERM_EXTRA */
-			0x00000004, /* EMC_PUTERM_WIDTH */
-			0x00000000, /* EMC_PUTERM_ADJ */
-			0x00000000, /* EMC_CDB_CNTL_1 */
-			0x00000000, /* EMC_CDB_CNTL_2 */
-			0x00000000, /* EMC_CDB_CNTL_3 */
-			0x00000002, /* EMC_QRST */
-			0x0000000d, /* EMC_QSAFE */
-			0x0000000e, /* EMC_RDV */
-			0x00000010, /* EMC_RDV_MASK */
-			0x00000942, /* EMC_REFRESH */
-			0x00000000, /* EMC_BURST_REFRESH_NUM */
-			0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */
-			0x00000001, /* EMC_PDEX2WR */
-			0x00000008, /* EMC_PDEX2RD */
-			0x00000001, /* EMC_PCHG2PDEN */
-			0x00000000, /* EMC_ACT2PDEN */
-			0x0000004e, /* EMC_AR2PDEN */
-			0x0000000e, /* EMC_RW2PDEN */
-			0x00000055, /* EMC_TXSR */
-			0x00000200, /* EMC_TXSRDLL */
-			0x00000004, /* EMC_TCKE */
-			0x00000005, /* EMC_TCKESR */
-			0x00000004, /* EMC_TPD */
-			0x0000000a, /* EMC_TFAW */
-			0x00000000, /* EMC_TRPAB */
-			0x00000005, /* EMC_TCLKSTABLE */
-			0x00000005, /* EMC_TCLKSTOP */
-			0x00000982, /* EMC_TREFBW */
-			0x00000002, /* EMC_FBIO_CFG6 */
-			0x00000000, /* EMC_ODT_WRITE */
-			0x00000000, /* EMC_ODT_READ */
-			0x1049b898, /* EMC_FBIO_CFG5 */
-			0x002c00a0, /* EMC_CFG_DIG_DLL */
-			0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-			0x00030000, /* EMC_DLL_XFORM_DQS0 */
-			0x00030000, /* EMC_DLL_XFORM_DQS1 */
-			0x00030000, /* EMC_DLL_XFORM_DQS2 */
-			0x00030000, /* EMC_DLL_XFORM_DQS3 */
-			0x00030000, /* EMC_DLL_XFORM_DQS4 */
-			0x00030000, /* EMC_DLL_XFORM_DQS5 */
-			0x00030000, /* EMC_DLL_XFORM_DQS6 */
-			0x00030000, /* EMC_DLL_XFORM_DQS7 */
-			0x00030000, /* EMC_DLL_XFORM_DQS8 */
-			0x00030000, /* EMC_DLL_XFORM_DQS9 */
-			0x00030000, /* EMC_DLL_XFORM_DQS10 */
-			0x00030000, /* EMC_DLL_XFORM_DQS11 */
-			0x00030000, /* EMC_DLL_XFORM_DQS12 */
-			0x00030000, /* EMC_DLL_XFORM_DQS13 */
-			0x00030000, /* EMC_DLL_XFORM_DQS14 */
-			0x00030000, /* EMC_DLL_XFORM_DQS15 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE0 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE1 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE2 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE3 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE4 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE6 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE7 */
-			0x00040000, /* EMC_DLL_XFORM_ADDR0 */
-			0x00040000, /* EMC_DLL_XFORM_ADDR1 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR2 */
-			0x00040000, /* EMC_DLL_XFORM_ADDR3 */
-			0x00040000, /* EMC_DLL_XFORM_ADDR4 */
-			0x00000000, /* EMC_DLL_XFORM_ADDR5 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE8 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE9 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE10 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE11 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE12 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE13 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE14 */
-			0x00000000, /* EMC_DLL_XFORM_QUSE15 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
-			0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
-			0x00040000, /* EMC_DLL_XFORM_DQ0 */
-			0x00040000, /* EMC_DLL_XFORM_DQ1 */
-			0x00040000, /* EMC_DLL_XFORM_DQ2 */
-			0x00040000, /* EMC_DLL_XFORM_DQ3 */
-			0x00004000, /* EMC_DLL_XFORM_DQ4 */
-			0x00004000, /* EMC_DLL_XFORM_DQ5 */
-			0x00004000, /* EMC_DLL_XFORM_DQ6 */
-			0x00004000, /* EMC_DLL_XFORM_DQ7 */
-			0x10000280, /* EMC_XM2CMDPADCTRL */
-			0x00000000, /* EMC_XM2CMDPADCTRL4 */
-			0x00111111, /* EMC_XM2CMDPADCTRL5 */
-			0x01231339, /* EMC_XM2DQSPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL2 */
-			0x00000000, /* EMC_XM2DQPADCTRL3 */
-			0x77ffc081, /* EMC_XM2CLKPADCTRL */
-			0x00000505, /* EMC_XM2CLKPADCTRL2 */
-			0x81f1f108, /* EMC_XM2COMPPADCTRL */
-			0x07070004, /* EMC_XM2VTTGENPADCTRL */
-			0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
-			0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
-			0x51451420, /* EMC_XM2DQSPADCTRL3 */
-			0x00514514, /* EMC_XM2DQSPADCTRL4 */
-			0x00514514, /* EMC_XM2DQSPADCTRL5 */
-			0x51451400, /* EMC_XM2DQSPADCTRL6 */
-			0x0000003f, /* EMC_DSR_VTTGEN_DRV */
-			0x0000009c, /* EMC_TXDSRVTTGEN */
-			0x00000000, /* EMC_FBIO_SPARE */
-			0x00020000, /* EMC_ZCAL_INTERVAL */
-			0x00000100, /* EMC_ZCAL_WAIT_CNT */
-			0x0170000e, /* EMC_MRS_WAIT_CNT */
-			0x0170000e, /* EMC_MRS_WAIT_CNT2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
-			0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
-			0xa1430000, /* EMC_AUTO_CAL_CONFIG */
-			0x00000000, /* EMC_CTT */
-			0x00000004, /* EMC_CTT_DURATION */
-			0x0000d3b3, /* EMC_CFG_PIPE */
-			0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */
-			0x00000009, /* EMC_QPOP */
-			0x0b000004, /* MC_EMEM_ARB_CFG */
-			0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RP */
-			0x00000007, /* MC_EMEM_ARB_TIMING_RC */
-			0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
-			0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
-			0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
-			0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
-			0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
-			0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
-			0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
-			0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
-			0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
-			0x06040202, /* MC_EMEM_ARB_DA_TURNS */
-			0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
-			0x76e50f08, /* MC_EMEM_ARB_MISC0 */
-			0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
-		},
-		{
-			0x00000005, /* MC_MLL_MPCORER_PTSA_RATE */
-			0x00000096, /* MC_PTSA_GRANT_DECREMENT */
-			0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
-			0x00ff0047, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
-			0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
-			0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
-			0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
-			0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
-			0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
-			0x00330049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
-			0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
-			0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
-			0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
-			0x00080039, /* MC_LATENCY_ALLOWANCE_HC_0 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
-			0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
-			0x00ff0041, /* MC_LATENCY_ALLOWANCE_GPU_0 */
-			0x00ff002c, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
-			0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
-			0x00ff0046, /* MC_LATENCY_ALLOWANCE_VIC_0 */
-			0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
-			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
-			0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
-			0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
-			0x00510034, /* MC_LATENCY_ALLOWANCE_VDE_1 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
-			0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
-			0x00ff0082, /* MC_LATENCY_ALLOWANCE_SATA_0 */
-			0x00ff0047, /* MC_LATENCY_ALLOWANCE_AFI_0 */
-		},
-		0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
-		0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
-		0x00000802, /* EMC_CTT_TERM_CTRL */
-		0x73340000, /* EMC_CFG */
-		0x0000088d, /* EMC_CFG_2 */
-		0x0004012c, /* EMC_SEL_DPD_CTRL */
-		0x002c0068, /* EMC_CFG_DIG_DLL */
-		0x80000321, /* Mode Register 0 */
-		0x80100002, /* Mode Register 1 */
-		0x80200000, /* Mode Register 2 */
-		0x00000000, /* Mode Register 4 */
-	},
-	{
-		0x15,       /* V5.0.2 */
 		"04_396000_1_V5.0.2_V0.3", /* DVFS table version */
 		396000,     /* SDRAM frequency */
 		870,        /* min voltage */